SDI IP Core User Guide

ID 683587
Date 8/20/2020
Document Table of Contents

3.3.3. Transmitter Transceiver Interface

Intel provides a transceiver interface, which interfaces the transceiver to the SDI function.
The transmitter transceiver interface implements the following functions:
  • Retiming from the parallel video clock domain to the transceiver transmitter clock domain.
  • Optional two-times oversampling for HD-SDI
  • Transmitter oversampling for SD-SDI
Table 13.  Transmitter Transceiver Interface Functions
Functions Description
Transmitter retiming

The parallel data input, txdata, to the transceiver must be synchronous and phase-aligned to the transceiver clock input, tx_coreclk. SD-SDI (and optionally HD-SDI) requires a retiming function, because of the oversampling logic. The transmitter uses a small 16×20 FIFO buffer for the retiming.

  • For HD-SDI, the FIFO buffer realigns the parallel video input to the transceiver clock, tx_coreclk. It is written on every tx_pclk, and read on every tx_coreclk.
  • For SD-SDI, the FIFO buffer also provides the rate conversion required by the transmitter oversampling logic. It is written on every other tx_pclk, using the SD-SDI data width conversion logic. It is read on every 5th or 11th tx_coreclk. This operation ensures that the transmitter oversampling logic is provided with a word of parallel video data on every 5th or 11th clock.
HD-SDI two-times oversampling

The two-time oversampling mode performs two-times oversampling and runs the transceiver at double rate, to give a better output jitter performance. This mode requires a higher rate reference clock.

SD-SDI transmitter oversampling

SD-SDI requires a 270-Mbps serial data rate, which is achieved by transmitting a 1,350 Mbps signal with each bit repeated five times. This process ensures that the transceiver runs at a supported frequency. In triple standard mode, bit are transmitted at 2,970 Mbps with each bit repeated 11 times.