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A.1. Specifying Timing Analyzer Constraints
To ensure your design meets timing and other requirements, you must constrain the design. This section provides the necessary steps to properly constrain your SDI design using the TimeQuest timing analyzer.
- Make sure that TimeQuest is specified as the default timing analyzer in the Timing Analysis Settings page of the Settings dialog box.
- Compile to create an initial design database before you specify timing constraints for your design. On the Processing menu, click Start Compilation.
A message indicates when compilation is complete.
- On the Tools menu, click TimeQuest Timing Analyzer.
- Create timing netlist, double-click Create Timing Netlist in the Tasks pane.
The timing netlist appears in the Report pane.
- Specify timing constraints and exceptions. To enter your timing requirements, you can use constraint entry dialog boxes or edit the previously created .sdc file.
- To save your constraints in an .sdc file, on the Constraints menu, click Write SDC File.
Figure 37. Constraints Design FlowThe figure below shows the flow of the constraint design.
Standard | Clocks | Units |
---|---|---|
SDI-SD | transceiver_data_rate | 270 Mbps |
tx_pclk | 27 MHz | |
tx_serial_refclk | 67.5 MHz | |
rx_sd_oversample_clk_in | 67.5 MHz | |
HD-SDI, HD-SDI dual link | transceiver_data_rate | 1,485 Mbps |
tx_pclk | 74.25 MHz | |
tx_serial_refclk | 74.25 MHz | |
rx_serial_refclk | 74.25 MHz | |
3G-SDI | transceiver_data_rate | 2,970 Mbps |
tx_pclk | 148.5 MHz | |
tx_serial_refclk | 148.5 MHz | |
rx_serial_refclk | 148.5 MHz | |
DR, TR | transceiver_data_rate | 2,970 Mbps |
tx_pclk | 148.5 MHz | |
tx_serial_refclk | 148.5 MHz | |
rx_serial_refclk | 148.5 MHz | |
Soft transceiver SDI | rx_sd_refclk_135 | 135 MHz |
rx_sd_refclk_337 | 337 MHz | |
rx_sd_refclk_337_90° | 337 MHz | |
tx_sd_refclk_270 | 270 MHz | |
tx_pclk | 27 MHz |
Standard | Set Multicycle Paths | set_clock_group | set_false_path (1) | Define Setup and Hold Relationship |
---|---|---|---|---|
SD-SDI | u_format* to u_format | tx_pclk, transmit_pcs0|clkout(gxb_tx_coreclk) | switchline, get_clocks receive_pcs0|clkout (gxb_rxclk) | — |
HD-SDI, HD-SDI dual link, 3G-SDI, DR, TR | — | rx_serial_refclk, receive_pcs0|clkout (gxb_rxclk) | switchline, get_clocks receive_pcs0|clkout (gxb_rxclk) | — |
tx_pclk, transmit_pcs0|clkout(gxb_tx_coreclk) | — | |||
Soft transceiver SDI | — | — | switchline, get_clocks receive_pcs0|clkout (gxb_rxclk) | Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero-degree clock to the 135-MHz clock |
Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock |
Standard | Minimize Timing Skew |
---|---|
SD-SDI, HD-SDI, HD-SDI dual link, 3G-SDI, DR, TR | — |
Soft transceiver SDI | I/O to sample_a|b|c|d[0] path as short as possible |