SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device Specify Clock Characteristics Set Multicycle Paths Specify Clocks that are Exclusive or Asynchronous Define the Setup and Hold Relationship between 135-MHz Clocks and 337.5-MHz Zero-degree Clocks Minimize Timing Skew
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

A.1.1. Constraints for SDI IP Core Using Stratix IV Device

These constraints are specifically used to constraint a duplex SDI IP core.

Specify Clock Characteristics

  • SD-SDI (rx_sd_oversample_clk_in = 67.5 MHz, tx_pclk = 27 MHz, tx_serial_refclk = 67.5 MHz) 
    create_clock -name {rx_sd_oversample_clk_in} -period 14.814 -waveform { 0.000 7.407 } [get_ports {rx_sd_oversample_clk_in}]
create_clock -name {tx_pclk} -period 14.814 -waveform { 0.000 7.407 } [get_ports {tx_pclk}]
create_clock -name {tx_serial_refclk} -period 14.814 -waveform { 0.000 7.407 } [get_ports {tx_serial_refclk}]
  • HD-SDI, HD-SDI dual link (rx_serial_refclk = 74.25 MHz, tx_pclk = 74.25 MHz, tx_serial_refclk = 74.25 MHz) 
    create_clock -name {rx_serial_refclk} -period 13.468 -waveform { 0.000 6.734 } [get_ports {rx_serial_refclk}]
create_clock -name {tx_pclk} -period 13.468 -waveform { 0.000 6.734 } [get_ports {tx_pclk}]
create_clock -name {tx_serial_refclk} -period 13.468 -waveform { 0.000 6.734 } [get_ports {tx_serial_refclk}]
  • 3G-SDI (rx_serial_refclk = 148.5 MHz, tx_pclk = 148.5 MHz, tx_serial_refclk = 148.5 MHz) 
    create_clock -name {rx_serial_refclk} -period 6.734 -waveform { 0.000 3.367 } [get_ports {rx_serial_refclk}]
create_clock -name {tx_pclk} -period 6.734 -waveform { 0.000 3.367 } [get_ports {tx_pclk}]
create_clock -name {tx_serial_refclk} -period 6.734 -waveform { 0.000 3.367 } [get_ports {tx_serial_refclk}]
  • Dual standard, triple standard SDI 
    create_clock -name {rx_serial_refclk} -period 6.734 -waveform { 0.000 3.367 } [get_ports {rx_serial_refclk}]
create_clock -name {tx_serial_refclk} -period 6.734 -waveform { 0.000 3.367 } [get_ports {tx_serial_refclk}]
create_clock -name {tx_pclk} -period 6.734 -waveform { 0.000 3.367 } [get_ports {tx_pclk}]
  • Soft transceiver SDI 
    create_clock -name {rx_sd_refclk_135} -period 7.407 -waveform { 0.000 3.703 } [get_ports {rx_sd_refclk_135}]
create_clock -name {rx_sd_refclk_337} -period 2.967 -waveform { 0.000 1.484 } [get_ports {rx_sd_refclk_337}]
create_clock -name {rx_sd_refclk_337_90deg} -period 2.967 -waveform { 0.000 1.484 } [get_ports {rx_sd_refclk_337_90deg}]
create_clock -name {tx_sd_refclk_270} -period 3.703 -waveform { 0.000 1.852 } [get_ports {tx_sd_refclk_270}]
create_clock -name {tx_pclk} -period 37.037 -waveform { 0.000 18.519 } [get_ports {tx_pclk}]

Set Multicycle Paths

In some device families and speed grades, timing violations may occur in the format block of the SDI IP core. For SD-SDI, these violations are multicycle, and you can fix by applying the following constraints to your design.
Note: These constraints apply only to SD-SDIs; the violations are single-cycle paths in other video standards. 
set_multicycle_path -setup -end -from [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|sdi_format:format_gen.u_format|*}] -to [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|sdi_format:format_gen.u_format|*}] 2
set_multicycle_path -hold -end -from [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|sdi_format:format_gen.u_format|*}] -to [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|sdi_format:format_gen.u_format|*}] 1

Specify Clocks that are Exclusive or Asynchronous

The SDI IP core may show timing violations in slower speed grade devices. These paths are not required to have fast timing, so you can use the following constraints to remove these timing paths. You can use the command set_clock_groups or set_false_path.
Note: The following SDC commands apply only for duplex core and Stratix IV devices; you must use the constraint entry dialog boxes to constrain the separate receiver or transmitter core and other device families.
  • SD-SDI 
    set_clock_groups -exclusive -group [get_clocks {tx_pclk}] -group [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|transmit_pcs0|clkout}]
set_false_path -from [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|switchline}] -to [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
  • HD-SDI, 3G-SDI, dual standard, triple standard SDI 
    set_clock_groups -exclusive -group [get_clocks {rx_serial_refclk}] -group [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}] 
set_clock_groups -exclusive -group [get_clocks {tx_pclk}] -group [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|transmit_pcs0|clkout}]
set_false_path -from [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|switchline}] -to [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
  • HD-SDI dual link (for the additional channel) 
    set_clock_groups -exclusive -group [get_clocks {rx_serial_refclk}] -group [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[1].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}] 
set_false_path -from [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|switchline}] -to [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[0].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]
set_clock_groups -exclusive -group [get_clocks {tx_pclk}] -group [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[1].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|transmit_pcs0|clkout}]
set_false_path -from [get_keepers {sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[1].u_txrx_port|switchline}] -to [get_clocks {sdi_megacore_top_inst|sdi_txrx_port_gen[1].u_txrx_port|gen_duplex_alt4gxb.u_gxb|alt4gxb_component|auto_generated|receive_pcs0|clkout}]

Define the Setup and Hold Relationship between 135-MHz Clocks and 337.5-MHz Zero-degree Clocks

These constraints apply only to soft transceiver SDI.
  • Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero-degree clock to the 135-MHz clock
  • Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock
    Use the set_min_delay command to specify an absolute minimum delay for a given path. 
    set_min_delay -from  [get_clocks {rx_sd_refclk_337}]  -to  [get_clocks {rx_sd_refclk_135}] 0.000
    Use the set_max_delay command to specify an absolute maximum delay for a given path. 
    set_max_delay -from [get_clocks {rx_sd_refclk_337}] -to [get_clocks {rx_sd_refclk_135}] 4.430

Minimize Timing Skew

You must minimize the timing skew among the paths from I/O pins to the four sampling registers.
  • sample_a[0]
  • sample_b[0]
  • sample_c[0]
  • sample_d[0]
To minimize the timing skew:
  • Manually place the sampling registers close to each other and to the serial input pin.
  • Because these four registers use four different clock domains, place two of the four registers in one LAB and the other two in another LAB.
  • Then, place the two chosen LABs within the same row regardless of the placement of the serial input.
  • Finally, do not place the four sampling registers at the immediate rows or columns next to the I/O, but at the second row or column next to the I/O bank. This location allows faster inter-LAB interconnections between I/O banks and their immediate rows or columns compared to core interconnection.
The following code is an example of a constraint, which you can set using the Intel® Quartus® Prime Assignment Editor: 
set_location_assignment PIN_99 -to sdi_rx
set_location_assignment LC_X32_Y17_N0 -to "sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst|serdes_s2p:u_s2p|sample_a[0]"
set_location_assignment LC_X33_Y17_N0 -to "sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst|serdes_s2p:u_s2p|sample_b[0]"
set_location_assignment LC_X32_Y17_N1 -to "sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst|serdes_s2p:u_s2p|sample_c[0]"
set_location_assignment LC_X33_Y17_N1 -to "sdi_megacore_top:sdi_megacore_top_inst|sdi_txrx_port:sdi_txrx_port_gen[0].u_txrx_port|soft_serdes_rx:rx_soft_serdes_gen.soft_serdes_rx_inst|serdes_s2p:u_s2p|sample_d[0]"
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