SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

3.4. Locking to the Incoming SDI Stream

The transceiver control state machine uses the presence (or absence) of TRSs on the stream to determine if SDI is being correctly received.

A single, valid TRS indicates to the control state machine that the receiver is acquiring some valid SDI samples. The control state machine only deasserts this flag when it does not detect any EAV sequences within the number of consecutive lines you specified. At this point, the controller state machine resets and performs the relock algorithm.

Figure 17. Locking AlgorithmThis figure shows how the controller state machine resets and performs the relock algorithm.

Because the aligner realigns to a new alignment if two consecutive TRSs with the same alignment are detected, this scheme allows for an SDI source switch and an alignment change without affecting the transceiver reset state machine.

The SDI MegaCore function also monitors the incoming EAV and SAV signals to ensure their spacing is consistent over a number of lines. The MegaCore function monitors by incrementing a counter on each incoming SDI word and storing the count values at which an EAV or SAV is detected. If the EAV and SAV spacing is consistent over 6 video lines, the MegaCore function indicates trs_locked on the rx_status[3] output.

An enhancement in the current SDI MegaCore function allows a number of missing EAV or SAV that you specify to be tolerated without deasserting the trs_locked signal.

For example, when you specify the Tolerance to consecutive missed EAV/SAV parameter to 2, one or two consecutive missing EAVs set a “missed” flag but do not cause the trs_locked signal to deassert. A good EAV in the correct position resets the “missed” flag.

The following figures show examples of the operation missing or misplaces TRS tolerance.

Figure 18. Single Missing EAVThis figure shows how a single missing EAV does not cause the trs_locked signal to deassert.
Figure 19. Two Consecutive Missing EAVsThis figure shows how two consecutive missing EAVs do not cause the trs_locked signal to deassert.
Figure 20. Three Consecutive Missing EAVsThis figure shows how three consecutive missing EAVs cause the trs_locked signal to deassert.

The frame_locked signal detects TRS EAV, inspects the transition of field (F) and vertical (V) synchronizations, and then counts the line number. The inspecting transitions on the F and V synchronizations provide the frame timing. The line count value is stored if there is a rising or falling edge on the F and V synchronizations through the frame. The stored count values are compared over multiple frames to make sure they are stable, before the frame_locked signal is asserted.

The frame_locked signal deasserts when there are bad F or V synchronizations, or when there is a rising edge from frame to frame. The frame_locked signal also deasserts when the trs_locked signal deasserts.

When the frame_locked signal is zero, the frame is invalid, and the receiver is not considered to receive reliable video data.

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