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Ixiasoft
A.2. Constraints for the SDI Soft Transceiver
These constraints apply to all supported device families that are configured to use a soft transceiver for their receivers.
Define the following setup and hold relationship between the 135-MHz clocks and the 337.5-MHz zero-degree clocks:
- Setup—1.5 clocks (4.43 ns) from the 337.5-MHz zero-degree clock to the 135-MHz clock
- Hold—zero clocks from the 337.5-MHz clock to the 135-MHz clock
If you choose to include the PLLs inside the IP core, modify the following constraints and apply them to your design. Alternatively, apply similar constraints to the clocks connected to the rx_sd_refclk_337 and rx_sd_refclk_135 signals on your SDI IP core.
Classic Timing Analyzer
Use the following constraints for the Classic timing analyzer:
set_instance_assignment -name SETUP_RELATIONSHIP "4.43 ns" -from “<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk0" -to "<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk2"
set_instance_assignment -name HOLD_RELATIONSHIP "0 ns" -from "<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk0" -to "<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk2"
TimeQuest Timing Analyzer
Use the following constraints for the TimeQuest timing analyzer:
set_max_delay 4.43 -from {<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk0} -to {<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk2}
set_min_delay 0 -from { <your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk0} -to {<your_megacore:your_megacore_inst>|sdi_megacore_top:sdi_megacore_top_inst|sdi_clocks:u_sdi_clocks|stratix_c2_pll_sclk:u_rx_pll|altpll:altpll_component|_clk2}