SDI IP Core User Guide

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ID 683587
Date 8/20/2020
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 1. SDI IP Core Overview 2. SDI IP Core Getting Started 3. Functional Description 4. SDI IP Core Signals 5. SDI IP Core User Guide Archives 6. Document Revision History for the SDI IP Core User Guide A. Constraints B. Clocking C. Receive and Retransmit
1. SDI IP Core Overview x
1.1. Release Information 1.2. Device Family Support 1.3. General Description 1.4. Resource Utilization
2. SDI IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.2. IP Catalog and Parameter Editor x
2.2.1. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.2.2. Parameterizing the SDI IP Core 2.2.3. SDI IP Core Parameters
3. Functional Description x
3.1. Transmitter 3.2. Receiver 3.3. Transceiver 3.4. Locking to the Incoming SDI Stream 3.5. SDI Receiving Video Format Specification
3.3. Transceiver x
3.3.1. Transmitter Clocks 3.3.2. Receiver Clocks 3.3.3. Transmitter Transceiver Interface 3.3.4. Receiver Transceiver Interface
4. SDI IP Core Signals x
4.1. SDI Clock Signals 4.2. SDI Interface Signals 4.3. SDI Status Signals 4.4. SDI Transceiver Dynamic Reconfiguration Signals
A. Constraints x
A.1. Specifying Timing Analyzer Constraints A.2. Constraints for the SDI Soft Transceiver
A.1. Specifying Timing Analyzer Constraints x
A.1.1. Constraints for SDI IP Core Using Stratix IV Device
B. Clocking x
B.1. Clocking Versions
C. Receive and Retransmit x
C.1. Loopback FIFO Buffer
Product Discontinuance Notification
1. SDI IP Core Overview
2. SDI IP Core Getting Started
3. Functional Description
4. SDI IP Core Signals
5. SDI IP Core User Guide Archives
6. Document Revision History for the SDI IP Core User Guide
A. Constraints
B. Clocking
C. Receive and Retransmit

2.2.3. SDI IP Core Parameters

You can set the SDI parameters using the IP catalog.

Parameter

Value

Description

Protocol Options

Video standard

SD-SDI, HD-SDI, 3G-SDI, HD-SDI dual link, dual or triple standard SDI

Sets the video standard.

  • SD-SDI—includes oversampling logic.
  • HD-SDI—switches in LN insertion and extraction and CRC generation and extraction blocks; selecting SD-SDI switches out LN insertion and extraction and CRC generation and extraction blocks.
  • Dual or triple rate SDI—includes the processing blocks for both SD-SDI and HD-SDI standards. In addition, logic for bypass paths and logic to automatically switch between the input standards is included.

Interface settings

Birectional, Receiver, Transmitter

Selects transceiver or protocol blocks or both.

When non-GX device is chosen, only SD-SDI protocol block is permitted.

If you want to generate HD-SDI or 3G-SDI protocol block, you must select a GX device.

Transceiver Option

Transceiver and Protocol Generate transceiver and protocol blocks, generate transceiver block only, or generate protocol block only Selects transceiver or protocol blocks or both.

When non-GX device is chosen, only SD-SDI protocol block is permitted.

If you want to generate HD-SDI or 3G-SDI protocol block, you must select a GX device.

Use soft logic for transceiver On or off

Uses soft logic to implement the transceiver logic, rather than using Stratix IV transceivers. SD-SDI only.

For example, if you run out of hard transceivers in your device, you can implement the function in soft logic. If you have spare transceivers in a device, you may wish to use them.

Starting channel number 0, 4, 8, ..., 156 Dual or triple standard only. Each dual or triple standard SDI must have a unique starting channel number.
Note: This parameter is not applicable for Arria V, Cyclone V, and Stratix V devices.
Use PLL reconfiguration for transceiver dynamic reconfiguration On or off Dual or triple standard, and Cyclone IV GX devices only. You must turn on this option if you select an EP4CGX110 or EP4CGX150 device.
Enable TX PLL select for 1/1.000 and 1/1.001 data rate reconfiguration On or off Enables an additional input port for transmitter serial reference clock.
Note: Available for Arria II and Stratix IV devices only.

Receiver/Transmitter Options

CRC error output

On or off

  • On: CRC monitoring (Not applicable for SD-SDI mode)
  • Off: No CRC monitoring (saves logic)

SDI synchronization output

On or off

Provides synchronization outputs.

Tolerance to consecutive missed EAV/SAV

0, 1, 2, ..., 15

Receiver protocol only. Allows you to set the number of consecutive missing EAVs to be tolerated in the incoming video. Specify a higher value if you want the receiver core to tolerate more errors.

If you want the receiver core not to tolerate any errors, set this option to 0.

Two times oversample mode

On or off

HD-SDI transmitter only. When turned on, runs the transceiver at twice the rate and has improved jitter performance.

Requires 148.5-MHz tx_serial_refclk reference clock.

Level Two Title