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Ixiasoft
A. Constraints
For the SDI IP core to work reliably, you must implement certain Intel® Quartus® Prime constraints.
- Specify clock characteristics
- Set timing exceptions such as false path, maximum and minimum delays, and multicycle path
- Minimize the timing skew among the paths from I/O pins to the four sampling registers
- Set the oversampling clock that the oversampling interface to 135 MHz uses as an independent clock domain