Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Public
Document Table of Contents

1.4.4. Wrapper Logic for PR Regions

Each persona of a PR region must implement the same input and output boundary ports. These ports act as the boundary between static and reconfigurable logic.

Implementing the same boundary ports ensures that all ports of a PR region remain stationary regardless of the underlying persona, so that the routing from the static logic does not change with different PR persona implementations.

Figure 8. Wire-LUTs at PR Region BoundaryThe Intel® Quartus® Prime software automatically instantiates a wire-LUT for each port of the PR region to lock down the same location for all instances of the PR persona.

If one persona of your PR region has a different number of ports than others, then you must create a wrapper so that the static region always communicates with this wrapper. In this wrapper, you can create dummy ports to ensure that all of the PR personas of a PR region have the same connection to the static region.

The sample code below each create two personas; persona_1 and persona_2 are different functions of one PR region. Note that one persona has a few dummy ports. The first example creates partial reconfiguration wrapper logic in Verilog HDL:

// Partial Reconfiguration Wrapper in Verilog HDL
module persona    //this module is persona_1 
  (
   input reset,  
   input [2:0] a, 
   input [2:0] b, 
   input [2:0] c,
   output [3:0] p,
   output [7:0] q
  );	
reg [3:0] p, q;
always@(a or b) 
  begin
    p = a + b ;
  end

always@(a or b or c or p)
  begin 
    q = (p*a - b*c )
  end
endmodule

module persona    //this module is persona_2 
(
 input reset,  
 input [2:0] a, 
 input [2:0] b, 
 input [2:0] c,   //never used in this persona
 output [3:0] p,
 output [7:0] q   //never assigned in this persona
);
reg [3:0] p, q;
always@(a or b) 
  begin
    p = a * b;    // note q is not assigned value in this persona
  end
endmodule

The following example creates partial reconfiguration wrapper logic in VHDL.

-- Partial Reconfiguration Wrapper in VHDL
-- this module is persona_1
entity persona is
  port( 
       a:in STD_LOGIC_VECTOR (2 downto 0);
	  b:in STD_LOGIC_VECTOR (2 downto 0);
	  c:in STD_LOGIC_VECTOR (2 downto 0);
	  p: out STD_LOGIC_VECTOR (3 downto 0);
	  q: out STD_LOGIC_VECTOR (7 downto 0)
       );
end persona;

architecture synth of persona is
    begin
      process(a,b)
        begin
		p <= a + b;
	   end process;

	 process (a, b, c, p)
        begin
          q <= (p*a - b*c);
        end process;
end synth;

-- this module is persona_2
entity persona is
  port( 
       a:in STD_LOGIC_VECTOR (2 downto 0);
       b:in STD_LOGIC_VECTOR (2 downto 0);
       c:in STD_LOGIC_VECTOR (2 downto 0);   --never used in this persona
       p:out STD_LOGIC_VECTOR (3 downto 0);
       q:out STD_LOGIC_VECTOR (7 downto 0) --never used in this persona
      );
end persona_2;

architecture synth of persona_2 is
  begin
    process(a, b)
      begin
	    p <= a *b; --note q is not assigned a value in this persona
	 end process;
end synth;