Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Document Table of Contents

1.1.1. Determining Resources for Partial Reconfiguration

You can use partial reconfiguration to configure only the resources such as LABs, embedded memory blocks, and DSP blocks in the FPGA core fabric that are controlled by configuration RAM (CRAM).

The functions in the periphery, such as GPIOs or I/O Registers, are controlled by I/O configuration bits and therefore cannot be partially reconfigured. Clock multiplexers for GCLK and QCLK are also not partially reconfigurable because they are controlled by I/O periphery bits.

Figure 1. Partially Reconfigurable Resources

These are the types of resource blocks in a Stratix V device.

Table 1.  Reconfiguration Modes of the FPGA Resource BlockThe following table describes the reconfiguration type supported by each FPGA resource block, which are shown in the figure.

Hardware Resource Block

Reconfiguration Mode

Logic Block

Partial Reconfiguration

Digital Signal Processing

Partial Reconfiguration

Memory Block

Partial Reconfiguration


Dynamic Reconfiguration ALTGX_Reconfig


Dynamic Reconfiguration ALTGX_Reconfig

Core Routing

Partial Reconfiguration

Clock Networks

Clock network sources cannot be changed, but a PLL driving a clock network can be dynamically reconfigured

I/O Blocks and Other Periphery

Not supported

The transceivers and PLLs in Altera FPGAs can be reconfigured using dynamic reconfiguration. For more information on dynamic reconfiguration, refer to the Dynamic Reconfiguration in Stratix V Devices chapter in the Stratix V Handbook.

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