Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
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1.12.5. Initializing M20K Blocks with a Double PR Cycle

When a PR region in your PR design contains an initialized M20K block and is reconfigured via AND/OR mode, your host logic must complete a double PR cycle, instead of a single PR cycle.

The PR IP has a double_pr input port, that must be asserted high when your PR region contains RAM blocks that must be initialized. The PR IP core handles the timing relations between the first and the second PR cycles of a Double PR operation. From your user logic, assert the double_pr signal when you assert the pr_start signal, and you deassert the double_pr signal when the freeze signal is deasserted by the PR IP. This method is also applicable in cases when the programming bitstream is compressed or encryted.