Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Public
Document Table of Contents

1.12.3. MLAB Blocks in PR designs

Stratix V devices include dual-purpose blocks called MLABs, which can be used to implement RAMs or LABs for user logic.

This section describes the restrictions while using MLAB blocks (sometimes also referred to as LUT-RAM) in Stratix V devices for your PR designs.

If your design uses MLABS as LUT RAM, you must use all available MLAB bits within the region.

Table 6.  RAM Implementation Restrictions SummaryThe following table shows a summary of the LUT-RAM Restrictions.

PR Mode

Type of memory in PR region

Stratix V Production

SCRUB mode

LUT RAM (no initial content)

OK

LUT ROM and LUT RAM with your initial content

OK

AND/OR mode

LUT RAM (no initial content)

While design is running: Write 1s to all locations before partial reconfiguration

At compile time: Explicitly initialize all memory locations in each new persona to 1 via initialization file (. mif).

LUT ROM and LUT RAM with your initial content

No

If your design does not use any MLAB blocks as RAMs, the following discussion does not apply. The restrictions listed below are the result of hardware limitations in specific devices.

Limitations with Stratix V Production Devices

When using SCRUB mode:

  • LUT-RAMs without initialized content, LUT-RAMs with initialized content, and LUT-ROMs can be implemented in MLABs within PR regions without any restriction.

When using AND/OR mode:

  • LUT-RAMs with initialized content or LUT-ROMs cannot be implemented in a PR region.
  • LUT-RAMs without initialized content in MLABs inside PR regions are supported with the following restrictions.
  • MLAB blocks contain 640 bits of memory. The LUT RAMs in PR regions in your design must occupy all MLAB bits, you should not use partial MLABs.
  • You must include control logic in your design with which you can write to all MLAB locations used inside PR region.
  • Using this control logic, write '1' at each MLAB RAM bit location in the PR region before starting the PR process. This is to work around a false EDCRC error during partial reconfiguration.
  • You must also specify a .mif that sets all MLAB RAM bits to '1' immediately after PR is complete.
  • ROMs cannot be implemented in MLABs (LUT-ROMs).
  • There are no restrictions to using MLABs in the static region of your PR design.

For more information, refer to the following documents in the Stratix V Handbook:

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