1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
188.8.131.52. Generating a .pmsf File from a .msf and .sof Input File 184.108.40.206. Generating a .rbf File from a .pmsf Input File 220.127.116.11. Create a Merged .msf File from Multiple .msf Files 18.104.22.168. Generating a Merged .pmsf File from Multiple .pmsf Files 22.214.171.124. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 126.96.36.199. Enable Bitstream Decryption Option
1.6.3. PR Control Signals Interface
You can use the Intel® Quartus® Prime Assembler and the Convert Programming File utilities to generate the different bitstreams necessary for full chip configuration and for partial reconfiguration. The programming bit-stream for partial reconfiguration contains the instructions (opcodes) as well as the configuration bits, necessary for reconfiguring each of the partial regions. When using an external host, the interface ports on the control block are mapped to FPGA pins. When using an internal host, these signals are within the core of the FPGA. When using the PR IP core as an internal host, connect the signals on the PR IP core appropirately as described in the Partial Reconfiguration IP Core User Guide and follow the instructions to start the PR process on the FPGA. If you are not using the PR IP core, make sure you understand these PR interface signals.
Figure 11. Partial Reconfiguration Interface Signals
These handshaking control signals are used for partial reconfiguration.
- PR_DATA: The configuration bitstream is sent on PR_ DATA[ 15:0], synchronous to the Clk.
- PR_DONE: Sent from CB to control logic indicating the PR process is complete.
- PR_READY: Sent from CB to control logic indicating the CB is ready to accept PR data from the control logic.
- CRC_Error: The CRC_Error generated from the device’s CRC block, is used to determine whether to partially reconfigure a region again, when encountering a CRC_Error.
- PR_ERROR: Sent from CB to control logic indicating an error during partial reconfiguration.
- PR_REQUEST: Sent from your control logic to CB indicating readiness to begin the PR process.
- corectl: Determines whether partial reconfiguration is performed internally or through pins.
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