Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Document Table of Contents

1.6.3. PR Control Signals Interface

You can use the Intel® Quartus® Prime Assembler and the Convert Programming File utilities to generate the different bitstreams necessary for full chip configuration and for partial reconfiguration. The programming bit-stream for partial reconfiguration contains the instructions (opcodes) as well as the configuration bits, necessary for reconfiguring each of the partial regions. When using an external host, the interface ports on the control block are mapped to FPGA pins. When using an internal host, these signals are within the core of the FPGA. When using the PR IP core as an internal host, connect the signals on the PR IP core appropirately as described in the Partial Reconfiguration IP Core User Guide and follow the instructions to start the PR process on the FPGA. If you are not using the PR IP core, make sure you understand these PR interface signals.
Figure 11. Partial Reconfiguration Interface Signals

These handshaking control signals are used for partial reconfiguration.

  • PR_DATA: The configuration bitstream is sent on PR_ DATA[ 15:0], synchronous to the Clk.
  • PR_DONE: Sent from CB to control logic indicating the PR process is complete.
  • PR_READY: Sent from CB to control logic indicating the CB is ready to accept PR data from the control logic.
  • CRC_Error: The CRC_Error generated from the device’s CRC block, is used to determine whether to partially reconfigure a region again, when encountering a CRC_Error.
  • PR_ERROR: Sent from CB to control logic indicating an error during partial reconfiguration.
  • PR_REQUEST: Sent from your control logic to CB indicating readiness to begin the PR process.
  • corectl: Determines whether partial reconfiguration is performed internally or through pins.

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