Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Public
Document Table of Contents

1.4.1. Design Partitions for Partial Reconfiguration

You must create design partitions for each PR region that you want to partially reconfigure. Optionally, you can also create partitions for the static parts of the design for timing preservation and/or for reducing compilation time.

There is no limit on the number of independent partitions or PR regions you can create in your design. You can designate any partition as a PR partition by enabling that feature in the LogicLock Regions window in the Intel® Quartus® Prime software.

Partial reconfiguration regions do not support the following IP blocks that require a connection to the JTAG controller:
  • In-System Memory Content EditorI
  • In-System Signals & Probes
  • Virtual JTAG
  • Nios II with debug module
  • Signal Tap tap or trigger sources
Note: PR partitions can contain only FPGA core resources, they cannot contain I/O or periphery elements.

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