Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Public
Document Table of Contents
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1.13. Document Revision History

Table 8.  Document Revision History

Date

Version

Changes

2017.11.06 17.1.0
  • Updated PR Bitstream Compression and Encryption topic to clarify FPGA family differences.
2015.11.02 15.1.0 Changed instances of Quartus II to Intel® Quartus® Prime .
2015.05.04 15.0.0
  • Correct Verilog HDL partial reconfiguration instantiation code example.
  • Added clear/set method to SCRUB mode option.
2015.12.15 14.1.0 Minor revisions to some topics to resolve design refinements:
  • Implementing Memories with Initialized Content
  • Instantiating the PR Control Block and CRC Block in Verilog HDL
  • Partial Reconfiguration Pins
June 2014 14.0.0 Minor updates to "Programming File Sizes for a Partial Reconfiguration Project" and code samples in "Freeze Logic for PR Regions" sections.

November 2013

13.1.0

Added support for merging multiple .msf and .pmsf files.

Added support for PR Megafunction.

Updated for revisions on timing requirements.

May 2013

13.0.0

Added support for encrypted bitstreams.

Updated support for double PR.

November 2012

12.1.0

Initial release.