- 184.108.40.206. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode
1. Design Planning for Partial Reconfiguration
|Intel® Quartus® Prime Design Suite 18.1|
|This document is part of a collection. You can download the entire collection as a single PDF: Intel® Quartus® Prime Standard Edition User Guides - Combined PDF link|
The Partial Reconfiguration (PR) feature in the Intel® Quartus® Prime software allows you to reconfigure a portion of the FPGA dynamically, while the remainder of the device continues to operate.
This chapter assumes a basic knowledge of Altera’s FPGA design flow, incremental compilation, and LogicLock™ region features available in the Intel® Quartus® Prime software. It also assumes knowledge of the internal FPGA resources such as logic array blocks (LABs), memory logic array blocks (MLABs), memory types (RAM and ROM), DSP blocks, clock networks.
The Intel® Quartus® Prime software supports the PR feature for the Intel® Stratix® V device family and Cyclone® V devices whose part number ends in "SC", for example, 5CGXFC9E6F35I8NSC.
An Example of a Partial Reconfiguration Design
Partial Reconfiguration Modes
Partial Reconfiguration Design Flow
Freeze Logic for PR Regions
Example of a Partial Reconfiguration Design with an External Host
Example Partial Reconfiguration with an Internal Host
Partial Reconfiguration Project Management
Programming Files for a Partial Reconfiguration Project
On-Chip Debug for PR Designs
Partial Reconfiguration Known Limitations
Document Revision History
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