Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Public
Document Table of Contents

1.4.3.3. Instantiating the PR Control Block and CRC Block in Verilog HDL

The following example  instantiates a PR control block in Verilog HDL, inside your top-level project, Chip_Top:
module Chip_Top (
                //User I/O signals (excluding PR related signals)
                ..
                ..
                //PR interface & configuration signals
                  pr_request,
                  pr_ready,
                  pr_done,
                  crc_error,
                  dclk,
                  pr_data,
                  init_done
                 ); 

//user I/O signal declaration
..
..
//PR interface and configuration signals declaration
  input   pr_request;
  output  pr_ready;
  output  pr_done;
  output  crc_error;
  input  dclk;
  input  [15:0] pr_data;
  output init_done

stratixv_prblock stratixv_prblock_inst
  (
    .clk      (dclk),
    .corectl  (1'b0),
    .prrequest(pr_request),  
    .data     (pr_data), 
    .error    (pr_error), 
    .ready    (pr_ready), 
    .done     (pr_done) 
  );

stratixv_crcblock stratixv_crcblock_inst
  (
    .clk      (clk),
    .shiftnld (1'b1),
    .crcerror (crc_error)
  );
endmodule

For more information on port connectivity for reading the Error Message Register (EMR), refer to the following application note.

Did you find the information on this page useful?

Characters remaining:

Feedback Message