Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Document Table of Contents Instantiating the PR Control Block and CRC Block in VHDL

This code example  instantiates a PR control block in VHDL, inside your top-level project, Chip_Top:
entity Chip_Top is port (
                         --User I/O signals (excluding PR related signals)
end Chip_Top;

-- Following shows the architecture behavior of Chip_Top

m_pr : stratixv_prblock
  port map( 
           clk       => dclk,
           corectl   =>'0', --1 - when using PR from inside
					   --0 - for PR from pins; You must also enable
					   -- the appropriate option in 
               Quartus® Prime settings 
           prrequest => pr_request,
           data      => pr_data,
           error     => pr_error,
           ready     => pr_ready,
           done      => pr_done
m_crc : stratixv_crcblock 
  port map(
	      shiftnld      =>  '1',       --If you want to read the EMR register when 
           clk          =>  dummy_clk, --error occurrs, refer to AN539 for the
							     --connectivity forthis signal. If you only want
							     --to detect CRC errors, but plan to take no
							     --further action, you can tie the shiftnld 
							     --signal to logical high.
           crcerror     =>  crc_error

For more information on port connectivity for reading the Error Message Register (EMR), refer to the following application note.

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