1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
18.104.22.168. Generating a .pmsf File from a .msf and .sof Input File 22.214.171.124. Generating a .rbf File from a .pmsf Input File 126.96.36.199. Create a Merged .msf File from Multiple .msf Files 188.8.131.52. Generating a Merged .pmsf File from Multiple .pmsf Files 184.108.40.206. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 220.127.116.11. Enable Bitstream Decryption Option
18.104.22.168. Component Declaration of the PR Control Block and CRC Block in VHDL
To instantiate the PR control block and the CRC block in your design manually, use this code sample containing the component declaration in VHDL. The PR function is performed from within the core (code located in Core_Top) and you must add additional ports to Core_Top to connect to both components. This example is in VHDL but you can create a similar instantiation in Verilog as well.
-- The Stratix V control block interface component stratixv_prblock is port( clk: in STD_LOGIC := '0'; corectl: in STD_LOGIC := '0'; data: in STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); done: out STD_LOGIC; error: out STD_LOGIC; externalrequest: out STD_LOGIC; prrequest: in STD_LOGIC := '0'; ready: out STD_LOGIC ); end component; -- The Stratix V CRC block for diagnosing CRC errors component stratixv_crcblock is port( shiftnld: in STD_LOGIC ; clk: in STD_LOGIC ; crcerror: out STD_LOGIC ); end component;
The following rules apply when connecting the PR control block to the rest of your design:
- The corectl signal must be set to ‘1’ (when using partial reconfiguration from core) or to ‘0’ (when using partial reconfiguration from pins).
- The corectl signal has to match the Enable PR pins option setting in the Device and Pin Options dialog box on the Setting page; if you have turned on Enable PR pins, then the corectl signal on the PR control block instantiation must be toggled to ‘0’.
- When performing partial reconfiguration from pins the Intel® Quartus® Prime software automatically assigns the PR unassigned pins. If you so choose, you can make pin assignments to all the dedicated PR pins in Pin Planner or Assignment Editor.
- When performing partial reconfiguration from core, you can connect the prblock signals to either core logic or I/O pins, excluding the dedicated programming pin such as DCLK.