ID 683499
Date 9/24/2018
Public

## 1.4.3.1. Component Declaration of the PR Control Block and CRC Block in VHDL

To instantiate the PR control block and the CRC block in your design manually, use this code sample containing the component declaration in VHDL. The PR function is performed from within the core (code located in Core_Top) and you must add additional ports to Core_Top to connect to both components. This example is in VHDL but you can create a similar instantiation in Verilog as well.
-- The Stratix V control block interface

component stratixv_prblock is
port(
clk: in STD_LOGIC := '0';
corectl: in STD_LOGIC := '0';
data: in STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
done: out STD_LOGIC;
error: out STD_LOGIC;
externalrequest: out STD_LOGIC;
prrequest: in STD_LOGIC := '0';
);
end component;

-- The Stratix V CRC block for diagnosing CRC errors

component stratixv_crcblock is
port(
shiftnld: in STD_LOGIC ;
clk: in STD_LOGIC ;
crcerror: out STD_LOGIC
);
end component;

The following rules apply when connecting the PR control block to the rest of your design:

• The corectl signal must be set to ‘1’ (when using partial reconfiguration from core) or to ‘0’ (when using partial reconfiguration from pins).
• The corectl signal has to match the Enable PR pins option setting in the Device and Pin Options dialog box on the Setting page; if you have turned on Enable PR pins, then the corectl signal on the PR control block instantiation must be toggled to ‘0’.
• When performing partial reconfiguration from pins the Intel® Quartus® Prime software automatically assigns the PR unassigned pins. If you so choose, you can make pin assignments to all the dedicated PR pins in Pin Planner or Assignment Editor.
• When performing partial reconfiguration from core, you can connect the prblock signals to either core logic or I/O pins, excluding the dedicated programming pin such as DCLK.