1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
126.96.36.199. Generating a .pmsf File from a .msf and .sof Input File 188.8.131.52. Generating a .rbf File from a .pmsf Input File 184.108.40.206. Create a Merged .msf File from Multiple .msf Files 220.127.116.11. Generating a Merged .pmsf File from Multiple .pmsf Files 18.104.22.168. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 22.214.171.124. Enable Bitstream Decryption Option
- 126.96.36.199. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode
1.2. An Example of a Partial Reconfiguration Design
A PR design is divided into two parts. The static region where the design logic does not change, and one or more PR regions.
Each PR region can have different design personas, that change with partial reconfiguration.
PR Region A has three personas associated with it; A1, A2, and A3. PR Region B has two personas; B1 and B2. Each persona for the two PR regions can implement different application specific logic, and using partial reconfiguration, the persona for each PR region can be modified without interrupting the operation of the device in the static or other PR region.
Figure 2. Partial Reconfiguration Project Structure
The following figure shows the top-level of a PR design, which includes a static region and two PR regions.
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