Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

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ID 683499
Date 9/24/2018
Public
Document Table of Contents
Document Table of Contents x
1. Design Planning for Partial Reconfiguration A. Intel® Quartus® Prime Standard Edition User Guides
1. Design Planning for Partial Reconfiguration x
1.1. Terminology 1.2. An Example of a Partial Reconfiguration Design 1.3. Partial Reconfiguration Modes 1.4. Partial Reconfiguration Design Flow 1.5. Freeze Logic for PR Regions 1.6. Implementation Details for Partial Reconfiguration 1.7. Example of a Partial Reconfiguration Design with an External Host 1.8. Example Partial Reconfiguration with an Internal Host 1.9. Partial Reconfiguration Project Management 1.10. Programming Files for a Partial Reconfiguration Project 1.11. On-Chip Debug for PR Designs 1.12. Partial Reconfiguration Known Limitations 1.13. Document Revision History
1.1. Terminology x
1.1.1. Determining Resources for Partial Reconfiguration
1.3. Partial Reconfiguration Modes x
1.3.1. SCRUB Mode 1.3.2. AND/OR Mode 1.3.3. Programming File Sizes for a Partial Reconfiguration Project
1.4. Partial Reconfiguration Design Flow x
1.4.1. Design Partitions for Partial Reconfiguration 1.4.2. Incremental Compilation Partitions for Partial Reconfiguration 1.4.3. Partial Reconfiguration Controller Instantiation in the Design 1.4.4. Wrapper Logic for PR Regions
1.4.3. Partial Reconfiguration Controller Instantiation in the Design x
1.4.3.1. Component Declaration of the PR Control Block and CRC Block in VHDL 1.4.3.2. Instantiating the PR Control Block and CRC Block in VHDL 1.4.3.3. Instantiating the PR Control Block and CRC Block in Verilog HDL
1.5. Freeze Logic for PR Regions x
1.5.1. Clocks and Other Global Signals for a PR Design 1.5.2. Floorplan Assignments for PR Designs
1.6. Implementation Details for Partial Reconfiguration x
1.6.1. Interface with the PR Control Block through a PR Host 1.6.2. Partial Reconfiguration Pins 1.6.3. PR Control Signals Interface 1.6.4. Reconfiguring a PR Region 1.6.5. Partial Reconfiguration Cycle Waveform
1.7. Example of a Partial Reconfiguration Design with an External Host x
1.7.1. Example of Using an External Host with Multiple Devices
1.9. Partial Reconfiguration Project Management x
1.9.1. Create Reconfigurable Revisions 1.9.2. Compiling Reconfigurable Revisions 1.9.3. Timing Closure for a Partial Reconfiguration Project 1.9.4. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs)
1.10. Programming Files for a Partial Reconfiguration Project x
1.10.1. Generating Required Programming Files 1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box
1.10.2. Generate PR Programming Files with the Convert Programming Files Dialog Box x
1.10.2.1. Generating a .pmsf File from a .msf and .sof Input File 1.10.2.2. Generating a .rbf File from a .pmsf Input File 1.10.2.3. Create a Merged .msf File from Multiple .msf Files 1.10.2.4. Generating a Merged .pmsf File from Multiple .pmsf Files 1.10.2.5. Enable Partial Reconfiguration Bitstream Decompression when Configuring Base Design SOF file in JTAG mode 1.10.2.6. Enable Bitstream Decryption Option
1.12. Partial Reconfiguration Known Limitations x
1.12.1. Memory Blocks Initialization Requirement for PR Designs 1.12.2. M20K RAM Blocks in PR Designs 1.12.3. MLAB Blocks in PR designs 1.12.4. Implementing Memories with Initialized Content 1.12.5. Initializing M20K Blocks with a Double PR Cycle
1.12.2. M20K RAM Blocks in PR Designs x
1.12.2.1. Limitations When Using Stratix V Production Devices
1. Design Planning for Partial Reconfiguration
A. Intel® Quartus® Prime Standard Edition User Guides

1.4. Partial Reconfiguration Design Flow

Partial reconfiguration is based on the revision feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the boundaries of the static region and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions, which contain the static region and describe the differences in the reconfigurable regions.

Two types of revisions are specific to partial reconfiguration: reconfigurable and aggregate. Both import the persona for the static region from the base revision. A reconfigurable revision generates personas for PR regions. An aggregate revision is used to combine personas from multiple reconfigurable revisions to create a complete design suitable for timing analysis.

The design flow for partial reconfiguration also utilizes the Intel® Quartus® Prime incremental compilation flow. To take advantage of incremental compilation for partial reconfiguration, you must organize your design into logical and physical partitions for synthesis and fitting. The partitions for which partial reconfiguration is enabled (PR partitions) must also have associated LogicLock assignments.

Revisions make use of personas, which are subsidiary archives describing the characteristics of both static and reconfigurable regions, that contain unique logic which implements a specific set of functions to reconfigure a PR region of the FPGA. Partial reconfiguration uses personas to pass this logic from one revision to another.

Figure 7. Partial Reconfiguration Design Flow

The PR design flow requires more initial planning than a standard design flow. Planning requires setting up the design logic for partitioning, and determining placement assignments to create a floorplan. Well-planned partitions can help improve design area utilization and performance, and make timing closure easier. You should also decide whether your system requires partial reconfiguration to originate from the FPGA pins or internally, and which mode you are using; the AND/OR mode or the SCRUB mode, because this influences some of the planning steps described in this section.

You must structure your source code or design hierarchy to ensure that logic is grouped correctly for optimization. Implementing the correct logic grouping early in the design cycle is more efficient than restructuring the code later. The PR flow requires you to be more rigorous about following good design practices. The guidelines for creating partitions for incremental compilation also include creating partitions for partial reconfiguration.

Use the following best practice guidelines for designing in the PR flow, which are described in detail in this section:

  • Determining resources for partial reconfiguration
  • Partitioning the design for partial reconfiguration
  • Creating incremental compilation partitions for partial reconfiguration
  • Instantiating the PR IP core in the design
  • Creating wrapper logic for PR regions
  • Creating freeze logic for PR regions
  • Planning clocks and other global signals for the PR design
  • Creating floorplan assignments for the PR design

Section Content
Design Partitions for Partial Reconfiguration
Incremental Compilation Partitions for Partial Reconfiguration
Partial Reconfiguration Controller Instantiation in the Design
Wrapper Logic for PR Regions

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