Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration

ID 683499
Date 9/24/2018
Document Table of Contents

1.1. Terminology

The following terms are commonly used in this chapter.
  • project: A Intel® Quartus® Prime project contains the design files, settings, and constraints files required for the compilation of your design.

  • revision: In the Intel® Quartus® Prime software, a revision is a set of assignments and settings for one version of your design. A Intel® Quartus® Prime project can have several revisions, and each revision has its own set of assignments and settings. A revision helps you to organize several versions of your design into a single project.

  • incremental compilation: This is a feature of the Intel® Quartus® Prime software that allows you to preserve results of previous compilations of unchanged parts of the design, while changing the implementation of the parts of your design that you have modified since your previous compilation of the project. The key benefits include timing preservation and compile time reduction by only compiling the logic that has changed.

  • partition: You can partition your design along logical hierarchical boundaries. Each design partition is independently synthesized and then merged into a complete netlist for further stages of compilation. With the Intel® Quartus® Prime incremental compilation flow, you can preserve results of unchanged partitions at specific preservation levels. For example, you can set the preservation levels at post-synthesis or post-fit, for iterative compilations in which some part of the design is changed. A partition is only a logical partition of the design, and does not necessarily refer to a physical location on the device. However, you may associate a partition with a specific area of the FPGA by using a floorplan assignment.

    For more information on design partitions, refer to the Best Practices for Incremental Compilation Partitions and Floorplan Assignments chapter in the Intel® Quartus® Prime Handbook.

  • LogicLock region: A LogicLock region constrains the placement of logic in your design. You can associate a design partition with a LogicLock region to constrain the placement of the logic in the partition to a specific physical area of the FPGA.

    For more information about LogicLock regions, refer to the Analyzing and Optimizing the Design Floorplan chapter in the Intel® Quartus® Prime Handbook Volume 2.

  • PR project: Any Intel® Quartus® Prime design project that uses the PR feature.

  • PR region: A design partition with an associated contiguous LogicLock region in a PR project. A PR project can have one or more PR regions that can be partially reconfigured independently. A PR region may also be referred to as a PR partition.

  • static region: The region outside of all the PR regions in a PR project that cannot be reprogrammed with partial reconfiguration (unless you reprogram the entire FPGA). This region is called the static region, or fixed region.

  • persona: A PR region has multiple implementations. Each implementation is called a persona. PR regions can have multiple personas. In contrast, static regions have a single implementation or persona.

  • PR control block: Dedicated block in the FPGA that processes the PR requests, handshake protocols, and verifies the CRC.

  • PR IP Core: Altera soft IP that can be used to configure the PR control block in the FPGA to mange the PR bitstream source.