MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents
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A.1. User Guide Revision History

Table 29.  MAX 10 FPGA Development Kit User Guide Revision History
Date Version Changes
September 2017 2017.09.07 Updated I/O standard voltage values in the On-Board Oscillators table in On-Board Oscillators
January 2017 2017.01.04 Corrected the following pin assignments in "10/100/1000 Ethernet PHY":
  • ENETA_TX_D1 on pin P5
  • ENETA_RX_ER on pin U2
  • ENET_MDIO on pin Y5
  • ENETB_TX_D2 on pin U3
  • ENETB_RS_D3 on pin R7
November 2015 2015.11.06
  • Updated "USB to UART" section.
  • Added note to "General User Input/Output section".
June 2015 2015.06.26
  • Updated "DDR3 Rev. B Board" section.
May 2015 2015.05.21
  • Added quad SPI content for Rev. B & C boards.
  • Corrected two PMOD pin signal names for Rev. B & C boards.
  • Changed four MAX 10 pins for DDR3 for Rev. C board only.
  • Changed two switch/signal names for SW2 for Rev. C board only.
  • Updated Switch and Jumper Settings section with VTAP description.
March 2015 2015.03.31 Initial release.