MAX 10 FPGA Development Kit User Guide

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ID 683460
Date 9/07/2017
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Board Test System 4. Board Components A. Additional Information
1. Overview x
1.1. General Description 1.2. Handling the Board
2. Getting Started x
2.1. Quartus II Web Edition Software 2.2. Installing the Development Kit 2.3. Installing the USB-Blaster Driver 2.4. Board Update Portal
3. Board Test System x
3.1. Using the Configure Menu 3.2. The System Info Tab 3.3. The GPIO Tab 3.4. The Flash Tab 3.5. The HSMC Tab 3.6. The DDR3 Tab 3.7. The ADC Tab 3.8. The HDMI Tab 3.9. The Sleep Mode Tab 3.10. The Power Monitor 3.11. The Clock Control
4. Board Components x
4.1. Board Overview 4.2. Featured Device 4.3. Configuration 4.4. Status Elements 4.5. Setup Elements 4.6. General User Input/Output 4.7. Clock Circuitry 4.8. Components and Interfaces 4.9. Memory 4.10. Power Distribution System
4.3. Configuration x
4.3.1. Using the Quartus II Programmer 4.3.2. Selecting the Internal Configuration Scheme 4.3.3. Switch and Jumper Settings
4.7. Clock Circuitry x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock Input/Output
4.8. Components and Interfaces x
4.8.1. 10/100/1000 Ethernet PHY 4.8.2. Digital-to-Analog Converter 4.8.3. HDMI Video Output 4.8.4. HSMC 4.8.5. Pmod Connectors 4.8.6. USB to UART
4.9. Memory x
4.9.1. DDR3 Rev. B Board 4.9.2. DDR3 Rev. C Board 4.9.3. Flash
A. Additional Information x
A.1. User Guide Revision History A.2. Compliance and Conformity Statements
A.2. Compliance and Conformity Statements x
A.2.1. CE EMI Conformity Caution
1. Overview
2. Getting Started
3. Board Test System
4. Board Components
A. Additional Information

4.8.4. HSMC

The high-speed mezzanine card (HSMC) interface is based on the Samtec 0.5 mm pitch, surface-mount QTH/QSH family of connectors. It is designed to support a full SPI-4.2 interface (17 LVDS channels) and 3 input and output clocks as well as SMBus and JTAG signals.

Since MAX 10 does not have transceiver channels, the HSMC clock-data-recovery channels are left unconnected.

The HSMC interface has programmable bi-directional I/O pins that can be used as 2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as various differential I/O standards including, but not limited to, LVDS, mini-LVDS, and RSDS with up to 17 full-duplex channels.

As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and single-ended I/O standards are only guaranteed to function when mixed according to either the generic single-ended pin-out or generic differential pin-out.

For more information about the HSMC specification such as signaling standards, signal integrity, compatible connectors, and mechanical information, refer to the High Speed Mezzanine Card (HSMC) Specification manual.

Table 21.  HSMC Schematic Signals
Board Reference (J2) Schematic Signal Name MAX 10 / MAX II Pin Number I/O Standard Description
33 HSMC_SDA AA19 2.5V CMOS inout Management serial data line
34 HSMC_SCL Y18 2.5V CMOS out Management serial clock line
35 HSMC_JTAG_TCK A9 (MAX II) part of chain JTAG clock
36 HSMC_JTAG_TMS A8 (MAX II) part of chain JTAG mode select
37 HSMC_JTAG_TDO A7 (MAX II) part of chain JTAG data out
38 HSMC_JTAG_TDI A6 (MAX II) part of chain JTAG data in
39 HSMC_CLK_OUT0 AA13 2.5V CMOS clock output clock output 0
40 HSMC_CLK_IN0 N4 2.5V CMOS clock in Clock input 0
41 HSMC_D0 Y7 2.5v CMOS inout Data bus
42 HSMC_D1 Y8 2.5v CMOS inout Data bus
43 HSMC_D2 AB2 2.5v CMOS inout Data bus
44 HSMC_D3 AB3 2.5v CMOS inout Data bus
47 HSMC_TX_D_P0 W3 2.5v CMOS inout or LVDS TX channels-p Data bus
48 HSMC_RX_D_P0 V5 2.5V CMOS inout or LVDS RX channels-p Data bus
49 HSMC_TX_D_N0 W4 2.5V CMOS inout or LVDS TX channels-n Data bus
50 HSMC_RX_D_N01 V4 2.5V CMOS inout or LVDS RX channels-n Data bus
53 HSMC_TX_D_P1 U7 2.5v CMOS inout or LVDS TX channels-p Data bus
54 HSMC_RX_D_P11 Y2 2.5V CMOS inout or LVDS RX channels-p Data bus
55 HSMC_TX_D_N1 U6 2.5V CMOS inout or LVDS TX channels-n Data bus
56 HSMC_RX_D_N11 Y1 2.5V CMOS inout or LVDS RX channels-n Data bus
59 HSMC_TX_D_P2 W6 2.5v CMOS inout or LVDS TX channels-p Data bus
60 HSMC_RX_D_P21 AA20 2.5V CMOS inout or LVDS RX channels-p Data bus
61 HSMC_TX_D_N2 W5 2.5V CMOS inout or LVDS TX channels-n Data bus
62 HSMC_RX_D_N21 AA1 2.5V CMOS inout or LVDS RX channels-n Data bus
65 HSMC_TX_D_P3 W8 2.5v CMOS inout or LVDS TX channels-p Data bus
66 HSMC_RX_D_P31 AB8 2.5V CMOS inout or LVDS RX channels-p Data bus
67 HSMC_TX_D_N3 W7 2.5V CMOS inout or LVDS TX channels-n Data bus
68 HSMC_RX_D_N31 AA8 2.5V CMOS inout or LVDS RX channels-n Data bus
71 HSMC_TX_D_P4 AA10 2.5v CMOS inout or LVDS TX channels-p Data bus
72 HSMC_RX_D_P41 AB9 2.5V CMOS inout or LVDS RX channels-p Data bus
73 HSMC_TX_D_N4 Y10 2.5V CMOS inout or LVDS TX channels-n Data bus
74 HSMC_RX_D_N41 AA9 2.5V CMOS inout or LVDS RX channels-n Data bus
77 HSMC_TX_D_P5 AA7 2.5v CMOS inout or LVDS TX channels-p Data bus
78 HSMC_RX_D_P51 AB7 2.5V CMOS inout or LVDS RX channels-p Data bus
79 HSMC_TX_D_N5 AA6 2.5V CMOS inout or LVDS TX channels-n Data bus
80 HSMC_RX_D_N51 AB6 2.5V CMOS inout or LVDS RX channels-n Data bus
83 HSMC_TX_D_P6 P10 2.5v CMOS inout or LVDS TX channels-p Data bus
84 HSMC_RX_D_P61 Y4 2.5V CMOS inout or LVDS RX channels-p Data bus
85 HSMC_TX_D_N6 R10 2.5V CMOS inout or LVDS TX channels-n Data bus
86 HSMC_RX_D_N61 Y3 2.5V CMOS inout or LVDS RX channels-n Data bus
89 HSMC_TX_D_P7 W10 2.5v CMOS inout or LVDS TX channels-p Data bus
90 HSMC_RX_D_P71 AB5 2.5V CMOS inout or LVDS RX channels-p Data bus
91 HSMC_TX_D_N7 W9 2.5V CMOS inout or LVDS TX channels-n Data bus
92 HSMC_RX_D_N71 AA5 2.5V CMOS inout or LVDS RX channels-n Data bus
95 HSMC_CLK_OUT_P1 P13 2.5V CMOS inout or LVDS clock out Clock output 1
96 HSMC_CLK_IN_P1 AA20 2.5V CMOS inout or LVDS clock in Clock input 1
97 HSMC_CLK_OUT_N1 R13 2.5V CMOS inout or LVDS clock out Clock output 1
98 HSMC_CLK_IN_N1 AB21 2.5V CMOS inout or LVDS clock in Clock input 1
101 HSMC_TX_D_P8 W14 2.5v CMOS inout or LVDS TX channels-p Data bus
102 HSMC_RX_D_P81 W13 2.5V CMOS inout or LVDS RX channels-p Data bus
103 HSMC_TX_D_N8 V13 2.5V CMOS inout or LVDS TX channels-n Data bus
104 HSMC_RX_D_N81 W12 2.5V CMOS inout or LVDS RX channels-n Data bus
107 HSMC_TX_D_P9 Y14 2.5v CMOS inout or LVDS TX channels-p Data bus
108 HSMC_RX_D_P91 AB15 2.5V CMOS inout or LVDS RX channels-p Data bus
109 HSMC_TX_D_N9 Y13 2.5V CMOS inout or LVDS TX channels-n Data bus
110 HSMC_RX_D_N91 AA14 2.5V CMOS inout or LVDS RX channels-n Data bus
113 HSMC_TX_D_P10 V16 2.5v CMOS inout or LVDS TX channels-p Data bus
114 HSMC_RX_D_P101 Y16 2.5V CMOS inout or LVDS RX channels-p Data bus
115 HSMC_TX_D_N10 U15 2.5V CMOS inout or LVDS TX channels-n Data bus
116 HSMC_RX_D_N101 AA15 2.5V CMOS inout or LVDS RX channels-n Data bus
119 HSMC_TX_D_P11 W16 2.5v CMOS inout or LVDS TX channels-p Data bus
120 HSMC_RX_D_P111 AA16 2.5V CMOS inout or LVDS RX channels-p Data bus
121 HSMC_TX_D_N11 V15 2.5V CMOS inout or LVDS TX channels-n Data bus
122 HSMC_RX_D_N111 AB16 2.5V CMOS inout or LVDS RX channels-n Data bus
125 HSMC_TX_D_P12 V17 2.5v CMOS inout or LVDS TX channels-p Data bus
126 HSMC_RX_D_P121 AB18 2.5V CMOS inout or LVDS RX channels-p Data bus
127 HSMC_TX_D_N12 W17 2.5V CMOS inout or LVDS TX channels-n Data bus
128 HSMC_RX_D_N121 AB17 2.5V CMOS inout or LVDS RX channels-n Data bus
131 HSMC_TX_D_P13 V12 2.5v CMOS inout or LVDS TX channels-p Data bus
132 HSMC_RX_D_P131 Y11 2.5V CMOS inout or LVDS RX channels-p Data bus
133 HSMC_TX_D_N13 V11 2.5V CMOS inout or LVDS TX channels-n Data bus
134 HSMC_RX_D_N131 W11 2.5V CMOS inout or LVDS RX channels-n Data bus
137 HSMC_TX_D_P14 P12 2.5v CMOS inout or LVDS TX channels-p Data bus
138 HSMC_RX_D_P141 AB11 2.5V CMOS inout or LVDS RX channels-p Data bus
139 HSMC_TX_D_N14 R12 2.5V CMOS inout or LVDS TX channels-n Data bus
140 HSMC_RX_D_N141 AB10 2.5V CMOS inout or LVDS RX channels-n Data bus
143 HSMC_TX_D_P15 AA12 2.5v CMOS inout or LVDS TX channels-p Data bus
144 HSMC_RX_D_P151 AB13 2.5V CMOS inout or LVDS RX channels-p Data bus
145 HSMC_TX_D_N15 AA11 2.5V CMOS inout or LVDS TX channels-n Data bus
146 HSMC_RX_D_N151 AB12 2.5V CMOS inout or LVDS RX channels-n Data bus
149 HSMC_TX_D_P16 Y17 2.5v CMOS inout or LVDS TX channels-p Data bus
150 HSMC_RX_D_P161 AB20 2.5V CMOS inout or LVDS RX channels-p Data bus
151 HSMC_TX_D_N16 AA17 2.5V CMOS inout or LVDS TX channels-n Data bus
152 HSMC_RX_D_N161 AB19 2.5V CMOS inout or LVDS RX channels-n Data bus
155 HSMC_CLK_OUT_P2 W15 2.5V CMOS inout or LVDS clock out Clock output 2
156 HSMC_CLK_IN_P2 V10 2.5V CMOS inout or LVDS clock in Clock input 2
157 HSMC_CLK_OUT_N2 V14 2.5V CMOS inout or LVDS clock out Clock output 2
158 HSMC_CLK_IN_N2 V9 2.5V CMOS inout or LVDS clock in Clock input 2
160 HSMC_PRSNTn AB14 2.5V Present
Related Information
1 MAX 10 doesn't have internal termination for LVDS RX. Install a 100-ohm resistor to support LVDS RX on HSMC.
Level Two Title