MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents

4.3. Configuration

The MAX 10 FPGA development kit supports two configuration methods:
  • Configuration by downloading a .sof file to the FPGA. Any power cycling of the FPGA or reconfiguration will power up the FPGA to a blank state.
  • Programming of the on-die FPGA Configuration Flash Memory (CFM) via a .pof file. Any power cycling of the FPGA or reconfiguration will power up the FPGA in self-configuration mode, using the files stored in the CFM.
You can use two different USB-Blaster™ hardware components to program the .sof or .pof files:
  • Embedded USB-Blaster II, type-B connector (J12).
  • JTAG header (J14). Use an external USB-Blaster, USB-Blaster II, or Ethernet Blaster download cable. The external download cable connects to the board through the JTAG header (J14).

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