MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
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3.5. The HSMC Tab

The HSMC Tab allows you to test the CMOS port.
Figure 10. The HSMC Tab
Control Description
Status Pattern sync: Shows the pattern synced or not synced state. The pattern is considered synced when the start of the data sequence is detected.
Port CMOS: The CMOS port is available for tests.
Data Type The following data types are available for analysis:
  • prbs7: Selects pseudo-random 7-bit sequences.
  • prbs15: Selects pseudo-random 15-bit sequences.
  • prbs23: Selects pseudo-random 23-bit sequences.
  • prbs31: Selects pseudo-random 31-bit sequences.
  • high_frequency: Divide by data pattern.
  • low_frequency: Divide by data pattern.
Error Control
  • Detected errors: Displays the number of data errors detected in the hardware.
  • Inserted errors: Displays the number of errors inserted into the transmit data stream.
  • Bit error rate (BER): Displays the bit error rate of the interface
  • Insert Error: Inserts a one-word error into the transmit data stream each time you click the button.
  • Clear: Resets the Detected errors and Inserted errors counters to zeroes.
Test Control
  • Stop: Resets the test.
  • Number of bits tested: Displays the number of bits tested since the last reset.