MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents

3.7. The ADC Tab

The ADC Tab (analog-to-digital) shows the real-time voltage values of all of the ADC input channels.

Figure 12. The ADC Tab

The two tables displayed on this tab, ADC 1 and ADC 2 are not editable. The following table shows where the channels connect to.

Dedicated Channel SMA Connector
ADC 1 ANAIN1_SMA(J18)
Channel0 ADC1_CH0(J20.1)
Channel1 ADC1_CH1(J20.3)
Channel2 ADC1_CH2(J20.5)
Channel3 ADC1_CH2(J20.7)
Channel4 ADC1_CH4(J20.11)
Channel5 ADC1_CH4(J20.13)
Channel6 ADC1_CH6(J20.15 or POT1)
Channel7 ADC1_CH7(J20.17)
Dedicated Channel SMA Connector
ADC 2 ANAIN2_SMA(J19)
Channel0 ADC1_CH0(J20.2)
Channel1 ADC1_CH1(J20.4)
Channel2 ADC1_CH2(J20.6)
Channel3 ADC1_CH2(J20.8)
Channel4 ADC1_CH4(J20.12)
Channel5 ADC1_CH4(J20.14)
Channel6 ADC1_CH6(J20.16)
Channel7 ADC1_CH7(J20.18)

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