MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents

4.6. General User Input/Output

User-defined I/O signal names, FPGA pin numbers, and I/O standards for the MAX® 10 FPGA development board.
Table 11.  User-Defined Push Button Signal Names
Board Reference Signal Name

MAX 10 FPGA

Pin Number

I/O Standard
S1 USER_PB0 L22 1.5 V
S2 USER_PB1 M21 1.5 V
S3 USER_PB2 M22 1.5 V
S4 USER_PB3 N21 1.5 V
Table 12.  User-Defined DIP Switch Schematic Signal Names
Board Reference Signal Name

MAX 10 FPGA

Pin Number

I/O Standard
SW1.1 USER_DIPSW0 H21 1.5 V
SW1.2 USER_DIPSW1 H22 1.5 V
SW1.3 USER_DIPSW2 J21 1.5 V
SW1.4 USER_DIPSW3 J22 1.5 V
SW2.1 USER_DIPSW4 G19 1.5 V
Table 13.  User LED (Green) Schematic Signal Names
Board Reference Signal Name

MAX 10 FPGA

Pin Number

I/O Standard
D15 USER_LED0 T20 1.5 V
D16 USER_LED1 U22 1.5 V
D17 USER_LED2 U21 1.5 V
D18 USER_LED3 AA21 1.5 V
D19 USER_LED4 AA22 1.5 V
For a MAX 10 Development Kit Baseline Pinout design vist the Altera Design Store.

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