MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents

4.9.3. Flash

The MAX 10 FPGA development kit provides a 512-Mb (megabit) quad SPI flash memory. Altera Generic QUAD SPI controller core is used by default to erase, read, and write quad SPI flash in reference designs of the Board Test System (BTS) installer.

If you use the parallel flash loader (PFL) IP to program the quad SPI flash, you need to generate a .pof (Programmer Object file) to configure the device.

Perform the following steps to generate a .pof file:

  1. Create a byte-order Quartus.ini file with the setting:

    PGMIO_SWAP_HEX_BYTE_DATA=ON

  2. Copy the .ini file to the project root directory and open the project with Quartus
  3. Open Convert Programming Files tool to generate the .pof file
Table 27.  Default Memory Map of the 512-Mb QSPI Flash
Block Description Size (KB) Address Range
Board test system scratch 512 0x03F8.0000 – 0x03FF.FFFF
User software 56640 0x0083.0000 – 0x03F7.FFFF
Factory software 4096 0x0043.0000 – 0x0082.FFFF
Zips(html, web content) 4096 0x0003.0000 – 0x0042.FFFF
Board information 64 0x0002.0000 – 0x0002.FFFF
Ethernet option bits 64 0x0001.0000 – 0x0001.FFFF
User design reset vector 64 0x0000.0000 – 0x0000.FFFF
Table 28.  Flash Pin Assignments, Schematic Signal Names, and Functions
Board Reference (U7) Schematic Signal Name Max 10 FPGA Pin Number I/O Standard Description
U7.7 QSPI_CSn C2 3.3V Chip select
U7.16 QSPI_CLK B2 3.3V Clock
U7.3 QSPI_RESETn W12 (MAX II) 3.3V Reset
U7.15 QSPI_IO0 C6 3.3V Address bus
U7.8 QSPI_IO1 C3 3.3V Address bus
U7.9 QSPI_IO2 C5 3.3V Address bus
U7.1 QSPI_IO3 B1 3.3V Address bus

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