MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents

4.8.1. 10/100/1000 Ethernet PHY

The MAX 10 FFPGA development kit supports 10/100/1000 base-T Ethernet using an external Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function.
Table 17.  Ethernet PHY A Pin Assignments, Signal Names and Functions
Board Reference (U9) Schematic Signal Name Max 10 FPGA Pin Number I/O Standard Description
U9.8 ENETA_GTX_CLK T5 2.5V CMOS 125 MHz RGMII TX clock
U9.4 ENETA_TX_CLK E10 3.3V LVCMOS 25/2.5 MHz MII TX clock
U9.11 ENETA_TX_D0 R5 2.5V CMOS RGMII TX data 0
U9.12 ENETA_TX_D1 P5 2.5V CMOS RGMII TX data 1
U9.14 ENETA_TX_D2 W1 2.5V CMOS RGMII TX data 2
U9.16 ENETA_TX_D3 W2 2.5V CMOS RGMII TX data 3
U9.9 ENETA_TX_EN R4 2.5V CMOS RGMII TX enable
U9.7 ENETA_TX_ER P4 2.5V CMOS MII TX error
U9.2 ENETA_RX_CLK P3 2.5V CMOS RGMII RX clock
U9.95 ENETA_RX_D0 N9 2.5V CMOS RGMII RX data 0
U9.92 ENETA_RX_D1 T1 2.5V CMOS RGMII RX data 1
U9.93 ENETA_RX_D2 N1 2.5V CMOS RGMII RX data 2
U9.91 ENETA_RX_D3 T3 2.5V CMOS RGMII RX data 3
U9.94 ENETA_RX_DV T2 2.5V CMOS RGMII RX valid
U9.3 ENETA_RX_ER U2 2.5V CMOS MII RX error
U9.28 ENETA_RESETN V8 2.5V CMOS Device reset
U9.23 ENETA_INTn V7 2.5V CMOS Management bus interrupt
U9.25 ENET_MDC Y6 2.5V CMOS MDI clock
U9.24 ENET_MDIO Y5 2.5V CMOS MDI data
U9.84 ENETA_RX_CRS N8 2.5V CMOS MII Carrier Sense
U9.83 ENETA_RX_COL P1 2.5V CMOS MII Collision
U9.55 CLK_25_ENET 2.5V CMOS 25 MHz Reference clock
U9.70 ENETA_LED_DUPLEX 2.5 V CMOS Duplex or collision LED
U9.76 ENETA_LED_LINK10 2.5 V CMOS 10 Mb link LED
U9.74 ENETA_LED_LINK100 R9 2.5V CMOS 100 Mb link LED
U9.73 ENETA_LED_LINK1000 2.5V CMOS 1000 Mb link LED
U9.58, 69 ENETA_LED_RX 2.5V CMOS RX data active LED
U9.61, 68 ENETA_LED_TX 2.5V CMOS TX data active LED
U9.29 ENETA_MDI_P0 2.5V CMOS MDI
U9.31 ENETA_MDI_N0 2.5V CMOS MDI
U9.33 ENETA_MDI_P1 2.5V CMOS MDI
U9.34 ENETA_MDI_N1 2.5V CMOS MDI
U9.39 ENETA_MDI_P2 2.5V CMOS MDI
U9.41 ENETA_MDI_N2 2.5V CMOS MDI
U9.42 ENETA_MDI_P3 2.5V CMOS MDI
U9.43 ENETA_MDI_N3 2.5V CMOS MDI
Table 18.  Ethernet PHY B Pin Assignments, Signal Names and Functions
Board Reference (U10) Schematic Signal Name Max 10 FPGA Pin Number I/O Standard Description
U10.8 ENETB_GTX_CLK T6 2.5V CMOS 125 MHz RGMII TX clock
U10.4 ENETB_TX_CLK E11 3.3V LVCMOS 25/2.5 MHz MII TX clock
U10.11 ENETB_TX_D0 U1 2.5V CMOS RGMII TX data 0
U10.12 ENETB_TX_D1 V1 2.5V CMOS RGMII TX data 1
U10.14 ENETB_TX_D2 U3 2.5V CMOS RGMII TX data 2
U10.16 ENETB_TX_D3 U4 2.5V CMOS RGMII TX data 3
U10.9 ENETB_TX_EN V3 2.5V CMOS RGMII TX enable
U10.7 ENETB_TX_ER U5 2.5V CMOS MII TX error
U10.2 ENETB_RX_CLK R3 2.5V CMOS RGMII RX clock
U10.95 ENETB_RX_D0 P8 2.5V CMOS RGMII RX data 0
U10.92 ENETB_RX_D1 M1 2.5V CMOS RGMII RX data 1
U10.93 ENETB_RX_D2 M2 2.5V CMOS RGMII RX data 2
U10.91 ENETB_RX_D3 R7 2.5V CMOS RGMII RX data 3
U10.94 ENETB_RX_DV R1 2.5V CMOS RGMII RX valid
U10.3 ENETB_RX_ER R2 2.5V CMOS MII RX error
U10.28 ENETB_RESETn AB4 2.5V CMOS Device reset
U10.23 ENETB_INTn AA3 2.5V CMOS Management bus interrupt
U10.25 ENET_MDC Y6 2.5V CMOS MDI clock
U10.24 ENET_MDIO Y5 2.5V CMOS MDI data
U10.84 ENETB_RX_CRS N3 2.5V CMOS MII Carrier Sense
U10.83 ENETB_RX_COL N2 2.5V CMOS MII Collision
U10.55 CLK_25_ENET 2.5V CMOS 25 MHz Reference clock
U10.70 ENETB_LED_DUPLEX 2.5V CMOS Duplex or collision LED
U10.76 ENETB_LED_LINK10 2.5V CMOS 10 Mb link LED
U10.74 ENETB_LED_LINK100 P9 2.5V CMOS 100 Mb link LED
U10.73 ENETB_LED_LINK1000 2.5V CMOS 1000 Mb link LED
U10.58, 69 ENETB_LED_RX 2.5V CMOS RX data active LED
U10.61, 65, 68 ENETB_LED_TX 2.5V CMOS TX data active LED
U10.29 ENETB_MDI_P0 2.5V CMOS MDI
U10.31 ENETB_MDI_N0 2.5V CMOS MDI
U10.33 ENETB_MDI_P1 2.5V CMOS MDI
U10.34 ENETB_MDI_N1 2.5V CMOS MDI
U10.39 ENETB_MDI_P2 2.5V CMOS MDI
U10.41 ENETB_MDI_N2 2.5V CMOS MDI
U10.42 ENETB_MDI_P3 2.5V CMOS MDI
U10.43 ENETB_MDI_N3 2.5V CMOS MDI

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