MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Document Table of Contents

3.6. The DDR3 Tab

The DDR3 Tab allows you to test the DDR3 by reading and writing to a selected amount of addresses.
Figure 11. The DDR3 Tab
Control Description
Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start:
  • Write, Read, and Total performance bars—Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve.
  • Write (MBps), Read (MBps), and Total (MBps)—Show the number of bytes of data analyzed per second.
  • Data bus: 72 bits (8 bits ECC) wide and the frequency is 1066 MHz double data rate. 2133 Megabits per second (Mbps) per pin. Equating to a theoretical maximum bandwidth of 136512 Mbps or 17064 MBps.
Error Control This control displays data errors detected during analysis and allows you to insert errors:
  • Detected errors—Displays the number of data errors detected in the hardware.
  • Inserted errors—Displays the number of errors inserted into the transaction stream.
  • Insert Error—Inserts a one-word error into the transaction stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear—Resets the Detected errors and Inserted errors counters to zeroes.
Number of Addresses to Write and Read Determines the number of addresses to use in each iteration of reads and writes.

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