MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Document Table of Contents

4.8.2. Digital-to-Analog Converter

The MAX 10 FPGA comes wtih one external 16 bit digital-to-analog converter (DAC) device with an SMA output.

The MAX 10 FPGA has two 12-bit successive approximation register (SAR) ADCs with sample rate of 1 MSps. One potentiometer is connected to ADC1_CH6 to function as a user-controlled DC, and it is connected to 2.5 V. To ensure performance evaluation of the ADCs, the MAX 10 development kit has separate analog supply and split partition for analog ground. An external 16-bit single channel DAC is connected to Bank 7 to enable closed loop evaluation. The DAC uses a 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with standard serial perifpheral interface (SPI), quad SPI, Microwire, and digital signal processor (DSP) interfaces.

Table 19.  Digital-to-Analog Converter Signals

Board Reference


Signal Name


Pin Number

I/O Standard Description
U33.5 DAC_SYNC U1.B10 3.3 V Level-triggered control input (active LOW). Frame synchronization signal for the input data.
U33.6 DAC_SCLK A7 3.3 V Serial clock input
U33.7 DAC_DIN A8 3.3 V Serial data input