MAX 10 FPGA Development Kit User Guide

ID 683460
Date 9/07/2017
Public
Document Table of Contents

4.7.2. Off-Board Clock Input/Output

The development board has input and output clocks which can be driven onto the board. The output clocks can be programmed to different levels and I/O standards according to the FPGA device’s specification.

Table 15.  Off-Board Clock Inputs
Source Schematic Signal Name I/O Standard MAX 10 FPGA Pin Number Description
HSMC HSMC_CLK_IN_N1 2.5 V AB21 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN_P1 2.5 V AA20 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN_N2 2.5 V V9 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN_P2 2.5 V V10 LVDS input from the installed HSMC cable or board.
HSMC HSMC_CLK_IN0 2.5 V N4 Single-ended input from the installed HSMC cable or board.
Table 16.  Off-Board Clock Outputs
Source Schematic Signal Name I/O Standard MAX 10 FPGA Pin Number Description
HSMC HSMC_CLK_OUT_N1 2.5 V R13 LVDS output.
HSMC HSMC_CLK_OUT_P1 2.5 V P13 LVDS output.
HSMC HSMC_CLK_OUT_N2 2.5 V V14 LVDS output.
HSMC HSMC_CLK_OUT_P2 2.5 V W15 LVDS output.
HSMC HSMC_CLK_OUT0 2.5 V AA13 FPGA CMOS output (or GPIO)

Did you find the information on this page useful?

Characters remaining:

Feedback Message