Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 1/11/2024
Document Table of Contents The Clock Control

The Intel® MAX® 10 FPGA 10M50 Evaluation Board Clock Control application sets the programmable oscillators to any frequency between 10 MHz and 200 MHz. It communicates with the MAX® II device on the board through the JTAG bus. The programmable oscillators are connected to the MAX® II device through a 2-wire serial bus.

To run the Clock Control GUI, follow these steps:

  1. Ensure you install the Intel® Quartus® Prime Standard Edition version 22.1 or later and the environment variable QUARTUS_ROOTDIR is set correctly.
  2. Connect the USB cable to the Intel® MAX® 10 FPGA 10M50 Evaluation Board and power cycle the board.
  3. Double click the Clock Controller application and the interface is shown in the figure below.
  4. Perform Default to set the default frequencies to the board: CLK0-24MHz, CLK1-24MHz, CLK2-125MHz, CLK3-100MHz.
  5. Perform Read operation to get the current frequency setup.
  6. If necessary, input new frequencies to each clock frequency fill-in box and perform Set New Freq to set the board to the input clock frequency setup.
  7. Select the Disable to disable any clock channel if needed.
Figure 8. The Si5338 Tab
Table 17.  The Clock Control Tab
Control Description
F_vco Displays the generating signal value of the voltage-controlled oscillator
Registers Displays the current frequencies for each oscillator
Frequency (MHz) Allows you to specify the frequency of the clock
Disable Disables each oscillators as required
Read Reads the current frequency setting for the oscillator associated with the active tab
Default Sets the frequency for the oscillator associated with the active tab back to its default value. This can be also be accompanied by power cycling the board.
Set New Freq Sets the programmable oscillator frequency for the selected clock to the value in the CLK0 and CLK3 controls. Frequency changes might take several milliseconds to take effect. You might see glitches on the clock during this time. Intel® recommends you to reset the FPGA logic after changing frequencies.
Note: Changing CLK0 of Si5338 affects the Clock/Power GUI. Once clock from Port CLK0 is used to drive the MAX® II device which is working as a 2-wire serial bus interface connected to Si570, Si5338 and power monitor.