Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

Download PDF
ID 683447
Date 1/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components A. Additional Information
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Intel® Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. On-Board Oscillators 3.7.2. Off-Board Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Document Revision History for the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide A.2. Safety and Regulatory Information A.3. Compliance Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
A. Additional Information

2.4. Factory Default Switch and Jumper Settings

Figure 2. Switch Locations and Default Settings (Board Top)
Table 3.  Default SW1 DIP Switch Settings
Board Reference Signal Name Function Default Position
SW1.1 USER_DIPSW0 User-Defined HIGH (OFF =1)
SW1.2 USER_DIPSW1 User-Defined HIGH (OFF =1)
SW1.3 USER_DIPSW2 User-Defined HIGH (OFF =1)
SW1.4 USER_DIPSW3 User-Defined HIGH (OFF =1)
Table 4.  Default SW2 DIP Switch Settings
Board Reference Signal Name Function Default Position
SW2.1 USER_DIPSW4 User-Defined HIGH (OFF =1)
SW2.2 USER_DIPSW5 User-Defined HIGH (OFF =1)
SW2.3 CONFIG_SEL CONFIG_SEL: Use this pin to choose CFM0, CFM1 or CFM2 image as the first boot image in dual-image configuration. If the CONFIG_SEL is set to low, the first boot image is CFM0 image. If CONFIG_SEL is set o high, the first boot image is CFM1 or CFM2 image. This pin is read before user mode and before the nSTATUS pin is asserted. LOW (ON =0)
SW2.4 VTAP_BYPASSn A virtual JTAG device is provided within the on-board Intel® FPGA Download Cable II, it provides access to diagnostic hardware and board identification information. The device shows up as an extra device on the JTAG chain with ID: 020D10DD. This switch removes the virtual JTAG device from the JTAG chain. HIGH (OFF =1)
Table 5.  Default J11 Jumper Settings
Jumper Function Setting
J11[1-2] Jumper for board DC adapter power option when R292 and R293 not installed Pins 1 and 2
J11[2-3] Jumper for board USB power option when R292 and R293 not installed. This is the default power jumper position. Pins 2 and 3
Level Two Title