MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

2.4. Factory Default Switch and Jumper Settings

Figure 2. Switch Locations and Default Settings (Board Top)
Table 2.  Default SW1 DIP Switch Settings
Board Reference Signal Name Function Default Position
SW1.1 USER_DIPSW0 User-Defined HIGH (OFF =1)
SW1.2 USER_DIPSW1 User-Defined HIGH (OFF =1)
SW1.3 USER_DIPSW2 User-Defined HIGH (OFF =1)
SW1.4 USER_DIPSW3 User-Defined HIGH (OFF =1)
Table 3.  Default SW2 DIP Switch Settings
Board Reference Signal Name Function Default Position
SW2.1 USER_DIPSW4 User-Defined HIGH (OFF =1)
SW2.2 USER_DIPSW5 User-Defined HIGH (OFF =1)
SW2.3 CONFIG_SEL CONFIG_SEL: Use this pin to choose CFM0, CFM1 or CFM2 image as the first boot image in dual-image configuration. If the CONFIG_SEL is set to low, the first boot image is CFM0 image. If CONFIG_SEL is set o high, the first boot image is CFM1 or CFM2 image. This pin is read before user mode and before the nSTATUS pin is asserted. LOW (ON =0)
SW2.4 VTAP_BYPASSn A virtual JTAG device is provided within the On-board USB-Blaster II, it provides access to diagnostic hardware and board identification information. The device shows up as an extra device on the JTAG chain with ID: 020D10DD. This switch removes the virtual JTAG device from the JTAG chain. HIGH (OFF =1)
Table 4.  Default J11 Jumper Settings
Jumper Function Setting
J11[1-2] Jumper for board DC adapter power option when R292 and R293 not installed Pins 1 and 2
J11[2-3] Jumper for board USB power option when R292 and R293 not installed. This is the default power jumper position. Pins 2 and 3

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