MAX® 10 FPGA 10M50 Evaluation Kit User Guide

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ID 683447
Date 11/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components 4. Document Revision History for the MAX® 10 FPGA 10M50 Evaluation Kit User Guide A. Additional Information
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. Onboard Oscillators 3.7.2. Offboard Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
4. Document Revision History for the MAX® 10 FPGA 10M50 Evaluation Kit User Guide
A. Additional Information

3.3.2. Selecting the Internal Configuration Scheme

For all MAX® 10 devices, except 10M02 device, there are total of 5 different modes you can select internal configuration. Refer to the Configuration Flash Memory Sectors Utilization for all MAX® 10 with Analog and Flash Feature Options figure of MAX® 10 FPGA Configuration User Guide .

The internal configuration scheme needs to be selected before design compilation. To select the configuration mode:
  1. Open the Quartus® Prime software and load a project using MAX® 10 device family.
  2. On the Assignments menu, click Settings. The Settings dialog box appears.
  3. In the Category list, select Device. The Device page appears.
  4. Click Device and Pin Options.
  5. In the Device and Pin Options dialog box, click the Configuration tab.
  6. In the Configuration Scheme list, select Internal Configuration.
  7. In the Configuration Mode list, select 1 out of 5 configuration modes. For the dual-boot feature:
    1. Must have a Dual Boot IP in the design, for example, in a Platform Designer (Standard) component.
    2. Choose Dual Compressed Images (512 Kbits UFM) for the Configuration Mode.
    3. Generate two .sof files above and convert them into one .pof file for CFM programming.
  8. Turn on Generate compressed bit-streams if needed, and click OK.
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