MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.8.5. MIPI CSI-2 Transmitter

The MAX 10 FPGA 10M50 evaluation kit supports one MIPI CSI-2 transmitter D-PHY to Leopard LI-MIPI-USB3-Tester module. This module includes one MIPI clock channel and four MIPI data channels. To interface the CSI-2 D-PHY compliant I/Os, the MAX 10 FPGA 10M50 Evaluation Kit uses one 1.8V HSTL signal pair and one 2.5V LVCMOS signal pair to support both high-speed and low-power nodes of one MIPI clock or data lane. The control signals (RST, SCLK, and SDATA) for LI-MIPI-USB3-Tester are implemented with both 1.8V and 3.3V options.

CAUTION:
The implemented D-PHY resistor values need to be adjusted based on user design. Simulation and signal quality measurement is required for optimal resistor values. Consult Application Note AN-754 for technical details on implementing the D-PHY passive circuits. The user must also install control signal path resistors (SCLK, SDATA, RST_IO) depending upon the I/O level desired.
Table 23.  MIPI CSI-2 Transmitter Pin Assignments, Signal Names and Functions
Source Schematic Signal Name Device/Pin Number I/O Standard Description

J1

(Cable needed to interface LI-MIPI-USB3-Tester module)

P/N: Molex 52559-3652
J1.26 MIPI_TX_CLK_HS_P MAX 10/ R2 1.8V HSTL Differential output clock (high-speed, positive terminal)
J1.25 MIPI_TX_CLK_HS_N MAX 10/ R1 1.8V HSTL Differential output clock (high-speed, negative terminal)
J1.26 MIPI_TX_CLK_LP_P MAX 10/ Y2 2.5V LVCMOS Differential output clock (low power, positive terminal)
J1.25 MIPI_TX_CLK_LP_N MAX 10/ Y1 2.5V LVCMOS Differential output clock (low power, negative terminal)
J1.29 MIPI_TX_DATA_HS_P1 MAX 10/ N1 1.8V HSTL Differential output data Lane1 (high speed, positive terminal)
J1.28 MIPI_TX_DATA_HS_N1 MAX 10/ P1 1.8V HSTL Differential output data Lane1 (high speed, negative terminal)
J1.29 MIPI_TX_DATA_LP_P1 MAX 10/ V5 2.5V LVCMOS Differential output data Lane1 (high speed, positive terminal)
J1.28 MIPI_TX_DATA_LP_N1 MAX 10/ V4 2.5V LVCMOS Differential output data Lane1 (high speed, negative terminal)
J1.23 MIPI_TX_DATA_HS_P2 MAX 10/ T2 1.8V HSTL Differential output data Lane2 (high speed, positive terminal)
J1.22 MIPI_TX_DATA_HS_N2 MAX 10/ T1 1.8V HSTL Differential output data Lane2 (high speed, negative terminal)
J1.23 MIPI_TX_DATA_LP_P2 MAX 10/ AB3 2.5V LVCMOS Differential output data Lane2 (high speed, positive terminal)
J1.22 MIPI_TX_DATA_LP_N2 MAX 10/ AB2 2.5V LVCMOS Differential output data Lane2 (low power, negative terminal)
J1.20 MAX_TX_DATA_HS_P3 MAX 10/ V1 1.8V HSTL Differential output data Lane3 (low power, positive terminal)
J1.19 MAX_TX_DATA_HS_N3 MAX 10/ U1 1.8V HSTL Differential output data Lane3 (high speed, negative terminal)
J1.20 MAX_TX_DATA_LP_P3 MAX 10/ AB5 2.5V LVCMOS Differential output data Lane3 (low power, positive terminal)
J1.19 MAX_TX_DATA_LP_N3 MAX 10/ AA5 2.5V LVCMOS Differential output data Lane3 (low power, negative terminal)
J1.17 MIPI_TX_DATA_HS_P4 MAX 10/ W2 1.8V HSTL Differential output data Lane4 (high speed, positive terminal)
J1.16 MIPI_TX_DATA_HS_N4 MAX 10/ W1 1.8V HSTL Differential output data Lane3 (high speed, negative terminal)
J1.17 MIPI_TX_DATA_HS_P4 MAX 10/ AB7 2.5V LVCMOS Differential output data Lane4 (low power, positive terminal)
J1.16 MIPI_TX_DATA_HS_N4 MAX 10/ AB6 2.5V LVCMOS Differential output data Lane4 (low power, negative terminal)
J1.14 MIPI_TX_CMOS_RST_1V8 MAX 10/ T3 1.8V LVCMOS Reset/Power Down (1.8V)
J1.14 MIPI_TX_CMOS_RST_3V3 MAX 10/ B10 3.3V LVCMOS Reset/Power Down (3.3V)
J1.13 MIPI_TX_CMOS_SDATA_1V8 MAX 10/ N2 1.8V LVCMOS Control Bus Data (1.8V)
J1.13 MIPI_TX_CMOS_SDATA_3V3 MAX 10/ H12 3.3V LVCMOS Control Bus Data (3.3V)
J1.12 MIPI_TX_CMOS_SCLK_1V8 MAX 10/ N3 1.8V LVCMOS Control Bus Clock (1.8V)
J1.12 MIPI_TX_CMOS_SCLK_3V3 MAX 10/ J11 3.3V LVCMOS Control Bus Clock (3.3V)
J1.11 MIPI_TX_CLK24MHz Clock Generator / U14.21 1.8V LVCMOS 24 MHz Reference Clock Output
J1.10 MIPI_TX_GPIO1 MAX 10/ U3 1.8V LVCMOS GPIO1
J1.9 MIPI_TX_GPIO2 MAX 10/ U2 1.8V LVCMOS GPIO2
J1.7 MIPI_TX_GPIO3 MAX 10/ U4 1.8V LVCMOS GPIO3
J1.6 MIPI_TX_GPIO4 MAX 10/ U5 1.8V LVCMOS GPIO4
J1.5 MIPI_TX_GPIO5 MAX 10/ V3 1.8V LVCMOS GPIO5
J1.33, J1.32 1.8V_MIPITX ---- 1.8V 1.8V
J1.36, J1.35, J1.34 3.3V_MIPITX ---- 3.3V 3.3V
J1.3, J1.4, J1.8, J1.15, J1.18, J1.21, J1.24, J1.27, J1.30, J1.31 GND   GND GND

To download MIPI reference designs for this Evaluation Kit, please contact your local Intel PSG (formerly Altera) sales team for assistance or check the DesignStore.

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