MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.8.7.2. Power Up Sequence

The figure below shows the power distribution system on the MAX 10 FPGA 10M50 Evaluation Board.

Figure 7. Power Tree
The power up sequence of the MAX 10 FPGA 10M50 Evaluation Board is shown in the table below:
Table 26.  Power Up Sequence Table
Power Up Sequence Device Output Voltage
1 EP5358HUI 1.8V
2 EP5348UI 1.2V
3 EM5329QI 3.3V
4 EP5384UI 2.5V
5 EN5339QI 1.2V

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