MAX® 10 FPGA 10M50 Evaluation Kit User Guide

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ID 683447
Date 11/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components 4. Document Revision History for the MAX® 10 FPGA 10M50 Evaluation Kit User Guide A. Additional Information
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. Onboard Oscillators 3.7.2. Offboard Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
4. Document Revision History for the MAX® 10 FPGA 10M50 Evaluation Kit User Guide
A. Additional Information

3.8.7.2. Power-Up Sequence

The figure below shows the power distribution system on the MAX® 10 FPGA 10M50 Evaluation Board.
Figure 9. Power Tree—EK-10M50F484 (Power Solution 1)

The power up sequence of the MAX® 10 FPGA 10M50 Evaluation Board is shown in the table below.

Table 27.  Power-Up Sequence—EK-10M50F484 (Power Solution 1)
Power-Up Sequence Device Output Voltage (V)
1 EP5358HUI 1.8
2 EP5348UI 1.2
3 EM5329QI 3.3
4 EP5384UI 2.5
5 EN5339QI 1.2
Figure 10. Power Tree—DK-DEV-10M50F484-C (Power Solution 2)
Table 28.  Power-Up Sequence—DK-DEV-10M50F484-C (Power Solution 2)
Power-Up Sequence Device Output Voltage (V)
1 MPM3804GG-C879-Z 1.8
2 MPM3804GG-C879-Z 1.2
3 MPM3632SGPQ-C879-Z 3.3
4 MPM3804GG-C879-Z 2.5
5 MPM3632SGPQ-C879-Z 1.2
Level Two Title