Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

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ID 683447
Date 1/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components A. Additional Information
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Intel® Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. On-Board Oscillators 3.7.2. Off-Board Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Document Revision History for the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide A.2. Safety and Regulatory Information A.3. Compliance Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
A. Additional Information

3.8.3.1. LPDDR2

The Intel® MAX® 10 FPGA provides full-speed support to a x16 LPDDR2 200-MHz interface by using a 1Gbit x 16 memory.
Table 21.  LPDDR2 Pin Assignments, Signal Names, and Functions
Board Reference (U2) Schematic Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard Description
U2.P3 LPDDR2_CA0 J22 1.2V HSUL Command/Address Bus Input
U2.N3 LPDDR2_CA1 J21 1.2V HSUL Command/Address Bus Input
U2.M3 LPDDR2_CA2 F22 1.2V HSUL Command/Address Bus Input
U2.M2 LPDDR2_CA3 H21 1.2V HSUL Command/Address Bus Input
U2.M1 LPDDR2_CA4 H22 1.2V HSUL Command/Address Bus Input
U2.G2 LPDDR2_CA5 D22 1.2V HSUL Command/Address Bus Input
U2.F2 LPDDR2_CA6 C22 1.2V HSUL Command/Address Bus Input
U2.F3 LPDDR2_CA7 E22 1.2V HSUL Command/Address Bus Input
U2.E3 LPDDR2_CA8 A21 1.2V HSUL Command/Address Bus Input
U2.E2 LPDDR2_CA9 B22 1.2V HSUL Command/Address Bus Input
U2.K1 LPDDR2_CKE E21 1.2V HSUL Clock Enable
U2.L1 LPDDR2_CSn G22 1.2V HSUL Chip Select
U2.J3 LPDDR2_CK D18 Differential 1.2V HSUL Differential Input Clock
U2.H3 LPDDR2_CKn E18 Differential 1.2V HSUL Differential Input Clock
U2.N8 LPDDR2_DQ0 N18 1.2V HSUL Data Bus Byte Lane 0
U2.M8 LPDDR2_DQ1 N20 1.2V HSUL Data Bus Byte Lane 0
U2.M7 LPDDR2_DQ2 M20 1.2V HSUL Data Bus Byte Lane 0
U2.M9 LPDDR2_DQ3 M14 1.2V HSUL Data Bus Byte Lane 0
U2.M6 LPDDR2_DQ4 M18 1.2V HSUL Data Bus Byte Lane 0
U2.L7 LPDDR2_DQ5 M15 1.2V HSUL Data Bus Byte Lane 0
U2.L8 LPDDR2_DQ6 L20 1.2V HSUL Data Bus Byte Lane 0
U2.L9 LPDDR2_DQ7 L18 1.2V HSUL Data Bus Byte Lane 0
U2.G9 LPDDR2_DQ8 K20 1.2V HSUL Data Bus Byte Lane 1
U2.G8 LPDDR2_DQ9 K19 1.2V HSUL Data Bus Byte Lane 1
U2.G7 LPDDR2_DQ10 K18 1.2V HSUL Data Bus Byte Lane 1
U2.F6 LPDDR2_DQ11 H19 1.2V HSUL Data Bus Byte Lane 1
U2.F9 LPDDR2_DQ12 H20 1.2V HSUL Data Bus Byte Lane 1
U2.F7 LPDDR2_DQ13 H18 1.2V HSUL Data Bus Byte Lane 1
U2.F8 LPDDR2_DQ14 J14 1.2V HSUL Data Bus Byte Lane 1
U2.E8 LPDDR2_DQ15 J18 1.2V HSUL Data Bus Byte Lane 1
U2.L6 LPDDR2_DQS0 L14 Differential 1.2V HSUL Data Strobe P Byte Lane 0
U2.L5 LPDDR2_DQS0n L15 Differential 1.2V HSUL Data Strobe N Byte Lane 0
U2.G6 LPDDR2_DQS1 K14 Differential 1.2V HSUL Data Strobe Byte P Lane 1
U2.G5 LPDDR2_DQS1n K15 Differential 1.2V HSUL Data Strobe Byte N Lane 1
U2.K5 LPDDR2_DM0 N19 1.2V HSUL Input Data Mask Byte Lane 0
U2.H5 LPDDR2_DM1 J15 1.2V HSUL Input Data Mask Byte Lane 1
U2.D3 LPDDR2_ZQ / 1.2V HSUL Output Drive Strength Calibration
CAUTION:
When you start your own design (with unique PCB layout) and intend to use the LPDDR2 interface, you should target the 10M50DCF484I6G or 10M50DAF484I6G. For other Intel® MAX® 10 parts that support LPDDR2 interfaces (include any 10M16 or higher density Intel® MAX® 10 device, with dual supply, F256 or higher pin-count, and –i6 speed grade), the Intel® Quartus® Prime access to these parts requires you to contact your local Intel® (formerly Altera) sales person to provide you with a special .ini variable.
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