MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.7.1. On-Board Oscillators

Figure 5. MAX 10 10M50 FPGA Evaluation Kit Clocks
Table 14.  On-Board Oscillators
Source Schematic Signal Name Frequency I/O Standard Device / Pin Number Application
U14 CLK24M 24.000 MHz 1.8 V CMOS MAX 10/M9 Programmable default 24 MHz clock for MAX 10
U14 OV5640_CLK24MHz 24.000 MHz 3.3 V CMOS 16 POS FFC connector / J3.12 Clock for MIPI RX OV5640 module
U14 CLK125M 125.000 MHz 3.3 V CMOS MAX 10/K22 Programmable default 125 MHz clock for PLL generating required clocks for LVDS GPIO interface
U14 CLK100M_LPDDR2 100.000 MHz 3.3 V CMOS MAX 10/E10 LPDDR2 clock
U15 CLK50M_MAX10 50.000 MHz 3.3 V CMOS MAX 10/J10 MAX 10 clock
U15 CLK50M_MAXII 50.000 MHz 3.3 V CMOS MAX II/L1 MAX II clock

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