MAX® 10 FPGA 10M50 Evaluation Kit User Guide

Download PDF
ID 683447
Date 11/14/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components 4. Document Revision History for the MAX® 10 FPGA 10M50 Evaluation Kit User Guide A. Additional Information
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Block Diagram 1.2. Feature Summary 1.3. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. Onboard Oscillators 3.7.2. Offboard Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
4. Document Revision History for the MAX® 10 FPGA 10M50 Evaluation Kit User Guide
A. Additional Information

3.8.6. MIPI CSI-2 Receiver

The MAX® 10 FPGA 10M50 Evaluation Kit supports MIPI CSI-2 receiver D-PHY to both Leopard Imaging OV10640 and UDOO OV5640 modules. The OV10640 module includes one MIPI clock channel and four MIPI data channels, while the OV5640 module has one MIPI clock channel and two MIPI data channels.

To interface MIPI CSI-2 D-PHY compliant I/O, the MAX® 10 FPGA 10M50 Evaluation Kit uses one 2.5 V LVDS signal pair to support high-speed mode and one 1.2 V HSTL signal pair to support low-power mode for each MIPI clock or data lane.

CAUTION:
The implemented D-PHY resistor values need to be adjusted based on user design. Simulation and signal quality measurement is required for optimal resistor values. Refer to AN-754: MIPI D-PHY Solution with Passive Resistor Networks in Altera® Low-Cost FPGAs for technical details on implementing the D-PHY passive circuits.
Table 25.  MIPI CSI-2 Receiver (for OV10640 module) Pin Assignments, Signal Names, and Functions
Source Schematic Signal Name Device/Pin Number I/O Standard Description

J2

(Cable needed to interface OV10640 module)

 P/N: 52559-3652
J2.11 OV10640_CLK_HS_P MAX® 10/P11 2.5 V LVDS Differential input clock (high speed, positive terminal)
J2.12 OV10640_CLK_HS_N MAX® 10/R11 2.5 V LVDS Differential input clock (high speed, negative terminal)
J2.11 OV10640_CLK_LP_P MAX® 10/T21 1.2 V HSTL Differential input clock (low power, positive terminal
J2.12 OV10640_CLK_LP_N MAX® 10/T22 1.2 V HSTL Differential input clock (low power, negative terminal
J2.8 OV10640_DATA_HS_P1 MAX® 10/AA20 2.5 V LVDS Differential input data Lane1 (high speed, positive terminal)
J2.9 OV10640_DATA_HS_N1 MAX® 10/AB21 2.5 V LVDS Differential input data Lane1 (high speed,negative terminal)
J2.8 OV10640_DATA_LP_P1 MAX® 10/P21 1.2 V HSTL Differential input data Lane1 (low power,positive terminal)
J2.9 OV10640_DATA_LP_N1 MAX® 10/N22 1.2 V HSTL Differential input data Lane1 (low power, negative terminal)
J2.14 OV10640_DATA_HS_P2 MAX® 10/AB20 2.5 V LVDS Differential input data Lane2 (high speed, positive terminal)
J2.15 OV10640_DATA_HS_N2 MAX® 10/AB19 2.5 V LVDS Differential input data Lane2 (high speed, negative terminal
J2.14 OV10640_DATA_LP_P2 MAX® 10/V21 1.2 V HSTL Differential input data Lane2 (low power,positive terminal)
J2.15 OV10640_DATA_LP_N2 MAX® 10/V22 1.2 V HSTL Differential input data Lane2 (low power, negative terminal
J2.17 OV10640_DATA_HS_P3 MAX® 10/AB18 2.5 V LVDS Differential input data Lane3 (high speed, positive terminal)
J2.18 OV10640_DATA_HS_N3 MAX® 10/AB17 2.5 V LVDS Differential input data Lane3 (high speed, negative terminal)
J2.17 OV10640_DATA_LP_P3 MAX® 10/Y22 1.2 V HSTL Differential input data Lane3 (low power, positive terminal)
J2.18 OV0640_DATA_LP_N3 MAX® 10/W22 1.2 V HSTL Differential input data Lane3 (low power, negative terminal)
J2.20 OV10640_DATA_HS_P4 MAX® 10/AA16 2.5 V LVDS Differential input data Lane4 (high speed, positive terminal)
J2.21 OV10640_DATA_HS_N4 MAX® 10/AB16 2.5 V LVDS Differential input data Lane4 (high speed, negative terminal)
J2.20 OV10640_DATA_LP_P4 MAX® 10/AA21 1.2 V HSTL Differential input data Lane4 (low power, positive terminal)
J2.21 OV10640_DATA_LP_N4 MAX® 10/AA22 1.2 V HSTL Differential input data Lane4 (low power, negative terminal)
J2.23 OV10640_CMOS_RST MAX® 10/P4 1.8 V LVCMOS Reset/Power down
J2.24 OV10640_CMOS_SDATA MAX® 10/N8 1.8 V LVCMOS Control Bus Data
J2.25 OV10640_CMOS_SCLK MAX® 10/P5 1.8 V LVCMOS Control Bus Clock
J2.26 OV10640_24MHz MAX® 10/N5 1.8 V LVCMOS 24 MHz Reference Clock Output
J2.27 OV10640_GYRO_INT MAX® 10/N9 1.8 V LVCMOS Gyroscope Programmable Interrupt
J2.28 OV10640_G_RDY MAX® 10/R4 1.8 V LVCMOS Gyroscope Data Ready
J2.31 OV10640_XM_INT1 MAX® 10/R7 1.8 V LVCMOS Accelerometer and magnetic sensor interrupt 1
J2.30 OV10640_XM_INT2 MAX® 10/R5 1.8 V LVCMOS Accelerometer and magnetic sensor interrupt 2
J2.32 OV10640_FSIN MAX® 10/P8 1.8 V LVCMOS Frame sync input
J2.4, J2.5 1.8V — 1.8 V 1.8V
J2.1, J2.2, J2.3 3.3V — 3.3 V 3.3V
J2.6, J2.7, J2.10, J2.13, J2.16, J2.19, J2.22, J2.29, J2.33, J2.34 GND — GND GND
Table 26.  MIPI CSI-2 Receiver (for OV5640 module) Pin Assignments, Signal Names, and Functions
Source Schematic Signal Name Device/Pin Number I/O Standard Description

J3

(Cable needed to interface OV5640 module)

 Wurth Electronics 68711614522
J3.6 OV5640_CLK_HS_P MAX® 10/V10 2.5 V LVDS Differential input clock (high speed, positive terminal)
J3.5 OV5640_CLK_HS_N MAX® 10/V9 2.5 V LVDS Differential input clock (high speed, negative terminal)
J3.6 OV5640_CLK_LP_P MAX® 10/R15 1.2 V HSTL Differential input clock (low power, positive terminal)
J3.5 OV5640_CLK_LP_N MAX® 10/R14 1.2 V HSTL Differential input clock (high speed, positive terminal)
J3.9 OV5640_DATA_HS_P1 MAX® 10/AB13 2.5 V LVDS Differential input data Lane1 (high speed,positive terminal)
J3.8 OV5640_DATA_HS_N1 MAX® 10/AB12 2.5 V LVDS Differential input data Lane1 (high speed,negative terminal)
J3.9 OV5640_DATA_LP_P1 MAX® 10/W19 1.2 V HSTL Differential input data Lane1 (low power,positive terminal)
J3.8 OV5640_DATA_LP_N1 MAX® 10/W20 1.2 V HSTL Differential input data Lane1 (low power,negative terminal)
J3.2 OV5640_DATA_HS_P2 MAX® 10/AB11 2.5 V LVDS Differential input data Lane2 (high speed,positive terminal)
J3.1 OV5640_DATA_HS_N2 MAX® 10/AB10 2.5 V LVDS Differential input data Lane2 (high speed,negative terminal)
J3.2 OV5640_DATA_LP_P2 MAX® 10/P15 1.2 V HSTL Differential input data Lane2 (low power,positive terminal)
J3.1 OV5640_DATA_LP_N2 MAX® 10/P14 1.2 V HSTL Differential input data Lane2 (low power,negative terminal)
J3.13 OV5640_SDC MAX® 10/M3 3.3 V LVCMOS Control Bus Clock
J3.14 OV5640_SDA MAX® 10/L1 3.3 V LVCMOS Control Bus Data
J3.12 OV5640_CLK24MHz Clock Generator / U14.18 3.3 V LVCMOS System Input Clock
J3.15 OV5640_CAM_RESETB MAX® 10/M4 3.3 V LVCMOS Reset
J3.11 OV5640_PWRON MAX® 10/L2 3.3 V LVCMOS Power Down
J3.16 3.3V — 3.3 V 3.3V
J3.3, J3.4, J3.7, J3.10 GND — GND GND

To download MIPI reference designs for this evaluation Kit, contact your Altera sales team for assistance or check the FPGA Design Store.

Level Two Title