Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

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ID 683447
Date 1/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview 2. Getting Started 3. Board Components A. Additional Information
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview x
1.1. Board Component Blocks 1.2. Supported Items Not Included with the Kit
2. Getting Started x
2.1. Powering the Kit 2.2. Installing the Intel® FPGA Download Cable II Driver 2.3. Handling the Kit 2.4. Factory Default Switch and Jumper Settings
3. Board Components x
3.1. Board Overview 3.2. Featured Device: Intel® MAX® 10 FPGA 3.3. Configuration 3.4. Status Elements 3.5. Setup Elements 3.6. General User Input/Output 3.7. Clock Circuitry 3.8. Components and Interfaces
3.3. Configuration x
3.3.1. Using the Intel® Quartus® Prime Programmer 3.3.2. Selecting the Internal Configuration Scheme
3.7. Clock Circuitry x
3.7.1. On-Board Oscillators 3.7.2. Off-Board Clock Input/Output 3.7.3. Clock Control GUI
3.7.3. Clock Control GUI x
3.7.3.1. The Clock Control
3.8. Components and Interfaces x
3.8.1. HDMI Video Output 3.8.2. Pmod Connectors 3.8.3. Memory 3.8.4. Flash 3.8.5. MIPI CSI-2 Transmitter 3.8.6. MIPI CSI-2 Receiver 3.8.7. Power Supply
3.8.3. Memory x
3.8.3.1. LPDDR2
3.8.7. Power Supply x
3.8.7.1. Power Options 3.8.7.2. Power-Up Sequence
A. Additional Information x
A.1. Document Revision History for the Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide A.2. Safety and Regulatory Information A.3. Compliance Information
A.2. Safety and Regulatory Information x
A.2.1. Safety Warnings A.2.2. Safety Cautions
1. Intel® MAX® 10 FPGA 10M50 Evaluation Kit Overview
2. Getting Started
3. Board Components
A. Additional Information

3.8.3. Memory

This section describes the evaluation board's memory interface support and also their signal names, types, and connectivity relative to the FPGA. A soft IP memory controller is required as part of the FPGA design. The memory controller can be a user supplied IP or IP available for purchase from Intel PSG (formerly Altera) or a partner.

Section Content
LPDDR2

Level Two Title