MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.8.3. Memory

This section describes the evaluation board's memory interface support and also their signal names, types, and connectivity relative to the FPGA. A soft IP memory controller is required as part of the FPGA design. The memory controller can be a user supplied IP or IP available for purchase from Intel PSG (formerly Altera) or a partner.

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