MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.3. Configuration

The MAX 10 10M50 Evaluation Kit supports two configuration methods:
  • Configuration by downloading a .sof file to the FPGA. Any subsequent power cycling of the FPGA or reconfiguration will power up the FPGA to a blank state.
  • Programming of the on-die FPGA Configuration Flash Memory (CFM) via a .pof file. Any power cycling of the FPGA or reconfiguration will power up the FPGA in self-configuration mode, using the files stored in the CFM
You can use two different USB-Blaster hardware components to program the .sof or .pof files:
  • Embedded USB-Blaster II, mini Type-B connector (J5)
  • JTAG header (J7). Use an external USB-Blaster, USB-Blaster II, or Ethernet Blaster download cable. The external download cable connects to the board through the JTAG header.

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