The Intel® MAX® 10 10M50 Evaluation Kit supports two configuration methods:
- Configuration by downloading a .sof file to the FPGA. Any subsequent power cycling of the FPGA or reconfiguration will power up the FPGA to a blank state.
- Programming of the on-die FPGA Configuration Flash Memory (CFM) via a .pof file. Any power cycling of the FPGA or reconfiguration will power up the FPGA in self-configuration mode, using the files stored in the CFM
- Embedded Intel® FPGA Download Cable II, mini Type-B connector (J5)
- JTAG header (J7). Use an external Intel® FPGA Download Cable, Intel® FPGA Download Cable II, or Intel FPGA Ethernet Download Cable. The external download cable connects to the board through the JTAG header.