MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.8.4. Flash

The MAX 10 10M50 Evaluation Kit provides a 512-Mb (megabit) quad SPI flash memory. Altera Generic QUAD SPI controller core is used by default to erase, read, and write quad SPI flash in reference designs of the Board Test System (BTS) installer.

If you use the parallel flash loader (PFL) IP to program the quad SPI flash, you need to generate a .pof (Programmer Object File) to configure the device.

Perform the following steps to generate a .pof file:
  1. Create a byte-order Quartus.ini file with the setting:

    PGMIO_SWAP_HEX_BYTE_DATA=ON

  2. Copy the .ini file to the project root directory and open the project with Quartus
  3. Open Convert Programming Files tool to generate the .pof file
Table 21.  Default Memory Map of the 512-Mb Quad SPI Flash
Block Description Size (KB) Address Range
Board Test System Scratch 512 0x03F8.0000 - 0x03FF.FFFF
User Software 56640 0x0083.0000 - 0x03F7.FFFF
Factory Software 4096 0x0043.0000 - 0x0082.FFFF
Board Information 64 0x0002.0000 - 0x0002.FFFF
User Design Reset Vector 64 0x0000.0000 - 0x0000.FFFF
Table 22.  Flash Pin Assignments, Schematic Signal Names, and Functions
Board Reference (U23) Signal Name Device/Pin Number I/O standard Description
U23.7 FLASH_CSn MAX 10/A8 3.3 V Chip select
U23.16 FLASH_CLK MAX 10/A9 3.3 V Clock
U23.3 FLASH_RESETn

MAX 10/B8

MAX II/U14

3.3 V Reset
U23.15 FLASH_D0 MAX 10/C9 3.3 V Address Bus
U23.8 FLASH_D1 MAX 10/C10 3.3 V Address Bus
U23.9 FLASH_D2 MAX 10/C11 3.3 V Address Bus
U23.1 FLASH_D3 MAX 10/A7 3.3 V Address Bus

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