MAX 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 9/30/2021
Public

3.7.2. Off-Board Clock Input/Output

The MAX 10 10M50 Evaluation Board has input and output clocks which can be driven onto the board. Resistor reworking might be needed for specific application.
Table 15.  Off-Board Clock Inputs and Outputs
Source Schematic Signal Name I/O Standard MAX 10 FPGA Description
J12 USER_CLKIN_N_MAX10 1.2 V K21 Single-ended clock input or user GPIO
J12 USER_CLKIN_P_MAX10 1.2 V K22 Single-ended clock input
J12 CLKOUT_LVDS_P 2.5 V V17 Single-ended clock output, or positive terminal for differential clock output to user GPIO
J12 CLKOUT_LVDS_N 2.5 V W17 Single-ended clock output, or negative terminal for differential clock output to user GPIO

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