3.7.3. Clock Control GUI
The Clock Control GUI application communicates over the JTAG bus to a test design running in the FPGA. It shares the JTAG bus with other applications like the Nios II debugger and the SignalTap® II Embedded Logic Analyzer. Because the Quartus II Programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out. Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer.
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