Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 1/11/2024
Document Table of Contents

3.7.3. Clock Control GUI

This kit includes a Clock Control GUI application.

The Clock Control GUI application communicates over the JTAG bus to a test design running in the FPGA. It shares the JTAG bus with other applications such as the the Signal Tap Logic Analyzer. Because the Intel® Quartus® Prime Programmer uses most of the bandwidth of the JTAG bus, other applications using the JTAG bus might time out. Ensure to close the other applications before attempting to reconfigure the FPGA using the Intel® Quartus® Prime Programmer.