Intel® MAX® 10 FPGA 10M50 Evaluation Kit User Guide

ID 683447
Date 1/11/2024
Document Table of Contents

3.5. Setup Elements

Table 9.  Board Settings DIP Switch and Jumper Schematic Signals
Board Reference Signal Name Device / Pin Number I/O Standard
SW2.3 MAX10_CONFIG_SEL Intel® MAX® 10/ H10 3.3V
SW2.4 MAX10_BYPASSn MAX II / B20 3.3V
Table 10.  Board Settings Push Button Signal Names
Board Reference Signal Name Intel® MAX® 10 FPGA Pin Number I/O Standard
S6 MAX10_nCONFIG H9 3.3V
S7 MAX10_RESETn D9 3.3V