1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
2.1.3. Read Enable
M9K memory blocks support the read enable feature for all memory modes.
|Create the read-enable port and perform a write operation with the read enable port deasserted.||The data output port retains the previous values from the most recent active read enable.|
|Activate the read enable during a write operation or do not create a read-enable signal.||The output port shows either the new data being written and the old data at that address, or a "Don't Care" value when read-during-write occurs at the same address location.|