| address_a |
Yes |
Address input to port A of the memory. The address_a port is required for all operation modes. |
| rden_a |
Optional |
Read enable input for address_a port. The rden_a port is supported depending on your selected memory mode and memory block. |
| address_b |
Optional |
Address input to port B of the memory. The address_b port is required if the operation_mode parameter is set to the following values:
- DUAL_PORT
- BIDIR_DUAL_PORT
|
| rden_b |
Optional |
Read enable input for address_b port. The rden_b port is supported depending on your selected memory mode and memory block. |
| clock |
Yes |
The following list describes which of your memory clock must be connected to the clock port, and port synchronization in different clock modes:
- Single clock—Connect your single source clock to clock port. All registered ports are synchronized by the same source clock.
- Read/Write—Connect your write clock to clock port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock.
- Input/Output—Connect your input clock to clock port. All registered input ports are synchronized by the input clock.
- Independent clock—Connect your port A clock to clock port. All registered input and output ports of port A are synchronized by the port A clock.
|
| addressstall_a |
Optional |
Address clock enable input to hold the previous address of address_a port for as long as the addressstall_a port is high. |
| addressstall_b |
Optional |
Address clock enable input to hold the previous address of address_b port for as long as the addressstall_b port is high. |
| inclock |
Yes |
The following list describes which of your memory clock must be connected to the inclock port, and port synchronization in different clock modes:
- Single clock—Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
- Read/Write—Connect your write clock to inclock port. The write clock synchronizes all registered ports related to write operation, such as data port, wraddress port, wren port, and byteena port.
- Input/Output—Connect your input clock to inclock port. The input clock synchronizes all registered input ports.
|
| outclock |
Yes |
The following list describes which of your memory clock must be connected to the outclock port, and port synchronization in different clock modes:
- Single clock—Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock.
- Read/Write—Connect your read clock to outclock port. The read clock synchronizes all registered ports related to read operation, such as rdaddress port, rdren port, and q port.
- Input/Output—Connect your output clock to outclock port. The output clock synchronizes the registered q port.
|
| inclocken |
Optional |
Clock enable input for inclock port. |
| outclocken |
Optional |
Clock enable input for outclock port. |
| aclr |
Optional |
Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr and wraddress_aclr. |