1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
188.8.131.52. Data Byte Output
|Deassert a byte-enable bit during a write cycle||The old data in the memory appears in the corresponding data-byte output.|
|Assert a byte-enable bit during a write cycle||The corresponding data-byte output depends on the Intel® Quartus® Prime software setting. The setting can be either the newly written data or the old data at that location.|
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