Intel® MAX™ 10 Embedded Memory User Guide

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ID 683431
Date 5/05/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Embedded Memory Overview 2. Intel® MAX® 10 Embedded Memory Architecture and Features 3. Intel® MAX® 10 Embedded Memory Design Consideration 4. RAM: 1-Port IP Core References 5. RAM: 2-PORT IP Core References 6. ROM: 1-PORT IP Core References 7. ROM: 2-PORT IP Core References 8. FIFO IP Core References 9. Shift Register (RAM-based) IP Core References 10. ALTMEMMULT IP Core References 11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide
2. Intel® MAX® 10 Embedded Memory Architecture and Features x
2.1. Intel® MAX® 10 Embedded Memory General Features 2.2. Intel® MAX® 10 Embedded Memory Operation Modes 2.3. Intel® MAX® 10 Embedded Memory Clock Modes 2.4. Intel® MAX® 10 Embedded Memory Configurations
2.1. Intel® MAX® 10 Embedded Memory General Features x
2.1.1. Control Signals 2.1.2. Parity Bit 2.1.3. Read Enable 2.1.4. Read-During-Write 2.1.5. Byte Enable 2.1.6. Packed Mode Support 2.1.7. Address Clock Enable Support 2.1.8. Asynchronous Clear
2.1.5. Byte Enable x
2.1.5.1. Byte Enable Controls 2.1.5.2. Data Byte Output 2.1.5.3. RAM Blocks Operations
2.1.7. Address Clock Enable Support x
2.1.7.1. Address Clock Enable During Read Cycle Waveform 2.1.7.2. Address Clock Enable During Write Cycle Waveform
2.1.8. Asynchronous Clear x
2.1.8.1. Resetting Registers in M9K Blocks
2.2. Intel® MAX® 10 Embedded Memory Operation Modes x
2.2.1. Supported Memory Operation Modes
2.3. Intel® MAX® 10 Embedded Memory Clock Modes x
2.3.1. Asynchronous Clear in Clock Modes 2.3.2. Output Read Data in Simultaneous Read and Write 2.3.3. Independent Clock Enables in Clock Modes
2.4. Intel® MAX® 10 Embedded Memory Configurations x
2.4.1. Port Width Configurations 2.4.2. Memory Configurations for Single-Port Modes 2.4.3. Memory Configurations for Dual-Port Modes 2.4.4. Maximum Block Depth Configuration
3. Intel® MAX® 10 Embedded Memory Design Consideration x
3.1. Implement External Conflict Resolution 3.2. Customize Read-During-Write Behavior 3.3. Consider Power-Up State and Memory Initialization 3.4. Control Clocking to Reduce Power Consumption 3.5. Selecting Read-During-Write Output Choices
3.2. Customize Read-During-Write Behavior x
3.2.1. Same-Port Read-During-Write Mode 3.2.2. Mixed-Port Read-During-Write Mode
3.2.2. Mixed-Port Read-During-Write Mode x
3.2.2.1. Mixed-Port Read-During-Write Operation with Dual Clocks
4. RAM: 1-Port IP Core References x
4.1. RAM: 1-Port IP Core Signals For Intel® MAX® 10 Devices 4.2. RAM: 1-Port IP Core Parameters For Intel® MAX® 10 Devices
5. RAM: 2-PORT IP Core References x
5.1. RAM: 2-Ports IP Core Signals (Simple Dual-Port RAM) For Intel® MAX® 10 Devices 5.2. RAM: 2-Port IP Core Signals (True Dual-Port RAM) for Intel® MAX® 10 Devices 5.3. RAM: 2-Port IP Core Parameters for Intel® MAX® 10 Devices
6. ROM: 1-PORT IP Core References x
6.1. ROM: 1-PORT IP Core Signals For Intel® MAX® 10 Devices 6.2. ROM: 1-PORT IP Core Parameters for Intel® MAX® 10 Devices
7. ROM: 2-PORT IP Core References x
7.1. ROM: 2-PORT IP Core Signals for Intel® MAX® 10 Devices 7.2. ROM: 2-Port IP Core Parameters For Intel® MAX® 10 Devices
8. FIFO IP Core References x
8.1. FIFO IP Core Signals for Intel® MAX® 10 Devices 8.2. FIFO IP Core Parameters for Intel® MAX® 10 Devices 8.3. FIFO Functional Timing Requirements 8.4. SCFIFO ALMOST_EMPTY Functional Timing
9. Shift Register (RAM-based) IP Core References x
9.1. Shift Register (RAM-based) IP Core Signals for Intel® MAX® 10 Devices 9.2. Shift Register (RAM-based) IP Core Parameters for Intel® MAX® 10 Devices
10. ALTMEMMULT IP Core References x
10.1. ALTMEMMULT IP Core Signals for Intel® MAX® 10 Devices 10.2. ALTMEMMULT IP Core Parameters for Intel® MAX® 10 Devices
1. Intel® MAX® 10 Embedded Memory Overview
2. Intel® MAX® 10 Embedded Memory Architecture and Features
3. Intel® MAX® 10 Embedded Memory Design Consideration
4. RAM: 1-Port IP Core References
5. RAM: 2-PORT IP Core References
6. ROM: 1-PORT IP Core References
7. ROM: 2-PORT IP Core References
8. FIFO IP Core References
9. Shift Register (RAM-based) IP Core References
10. ALTMEMMULT IP Core References
11. Document Revision History for the Intel® MAX® 10 Embedded Memory User Guide

5.3. RAM: 2-Port IP Core Parameters for Intel® MAX® 10 Devices

Table 20.  RAM: 2-Port IP Core Parameters for Intel® MAX® 10 Devices This table lists the IP core parameters applicable to Intel® MAX® 10 devices.
Option Legal Values Description
Parameter Settings: General
How will you be using the dual port RAM?
  • With one read port and one write port
  • With two read/write ports
 Specifies how you use the dual port RAM.
How do you want to specify the memory size?
  • As a number of words
  • As a number of bits
 Determines whether to specify the memory size in words or bits.
Parameter Settings: Widths/ Blk Type
How many <X>-bit words of memory? — Specifies the number of <X>-bit words.
Use different data widths on different ports On/Off Specifies whether to use different data widths on different ports.
Read/Write Ports When you select With one read port and one write port, the following options are available:
  • How wide should the ‘data_a’ input bus be?
  • How wide should the ‘q’ output bus be?
 1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 18, 32, 36, 64, 72, 108, 128, 144, 256, and 288 Specifies the width of the input and output ports.

The How wide should the ‘q’ output bus be? and the How wide should the ‘q_b’ output bus be? options are only available when you turn on the Use different data widths on different ports parameter.

When you select With two read/write ports, the following options are available:
  • How wide should the ‘q_a’ output bus be?
  • How wide should the ‘q_b’ output bus be?
What should the memory block type be?
  • Auto
  • M9K
  • LCs
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.

The LCs value is only available under the following conditions:

  • Turn on the With one read port and one write port option
  • Turn off Use different data widths on different ports option.
Option How should the memory be implemented?
  • Use default logic cell style
  • Use Stratix M512 emulation logic cell style
 Specifies the logic cell implementation options. This option is enabled only when you choose LCs memory type.
Set the maximum block depth to
  • Auto
  • 128
  • 256
  • 512
  • 1024
  • 2048
  • 4096
  • 8192
 Specifies the maximum block depth in words.
Parameter Settings: Clks/Rd, Byte En
What clocking method would you like to use? When you select With one read port and one write port, the following values are available:
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Dual clock: use separate ‘read’ and ‘write’ clocks
When you select With two read/write ports, the following options are available:
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Dual clock: use separate clocks for A and B ports
Specifies the clocking method to use.
  • Single clock—A single clock and a clock enable controls all registers of the memory block.
  • Dual Clock: use separate ‘input’ and ‘output’ clocks—An input clock controls all registers related to the data input to the embedded memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
  • Dual clock: use separate ‘read’ and ‘write’ clocks—A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers.
  • Dual clock: use separate clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
Create a ‘rden’ read enable signal On/Off
  • Available when you select With one read port and one write port option.
  • Specifies whether to create a read enable signal.
Create a ‘rden_a’ and ‘rden_b’ read enable signal On/Off
  • Available when you select With two read/write ports option.
  • Specifies whether to create a read enable signal for Port A and B.
Byte Enable Ports Create byte enable for port A On/Off Specifies whether to create a byte enable for Port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written.
Parameter Settings: Regs/Clkens/Aclrs  
Which ports should be registered?

When you select With one read port and one write port, the following options are available:

  • Write input ports ‘data_a’, ‘wraddress_a’, and ‘wren_a’
  • Read input ports 'rdaddress' and 'rden'
  • Read output port(s) ‘q_a’ and 'q_b'
When you select With two read/write ports, the following options are available:
  • Write input ports ‘data_a’, ‘wraddress_a’, and ‘wren_a’ write input ports
  • Read output port(s) ‘q’_a and ‘q_b’
 On/Off Specifies whether to register the read or write input and output ports.
More Option When you select With one read port and one write port, the following options are available:
  • ‘q_b’ port
When you select With two read/write ports, the following options are available:
  • ‘q_a’ port
  • ‘q_b’ port
 On/Off The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports.
Create one clock enable signal for each clock signal. On/Off Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Option When you select With one read port and one write port, the following option is available:
  • Clock enable options
    • Clock enable options: Use clock enable for write input registers
  • Address options
    • Create an ‘wr_addressstall’ input port.
    • Create an ‘rd_addressstall’ input port.
When you select With two read /write ports, the following options are available:
  • Clock enable options
    • Use clock enable for port A input registers
    • Use clock enable for port A output registers
  • Address options
    • Create an ‘addressstall_a’ input port.
    • Create an ‘addressstall_b’ input port.
On/Off
  • Clock enable options—Clock enable for port B input and output registers are turned on by default. You only need to specify whether to use clock enable for port A input and output registers.
  • Address options—Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
Create an ‘aclr’ asynchronous clear for the registered ports. On/Off Specifies whether to create an asynchronous clear port for the registered ports.
More Option When you select With one read port and one write port, the following options are available:
  • ‘rdaddress’ port
  • ‘q_b’ port
When you select With two read /write ports, the following options are available:
  • ‘q_a’ port
  • ‘q_b’ port
 On/Off Specifies whether the raddress, q_a, and q_b ports are cleared by the aclr port.
Parameter Settings: Output 1
Mixed Port Read-During-Write for Single Input Clock RAM When you select With one read port and one write port, the following option is available:
  • How should the q output behave when reading a memory location that is being written from the other port?
When you select With two read /write ports, the following option is available:
  • How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port?
  • Old memory contents appear
  • I do not care (the outputs will be undefined)
 Specifies the output behavior when read-during-write occurs.
  • Old memory contents appear— The RAM outputs reflect the old data at that address before the write operation proceeds.
  • I do not care—This option functions differently when you turn it on depending on the following memory block type you select:
    • When you set the memory block type to Auto or M9K, the RAM outputs ‘don't care’ or “unknown” values for read-during-write operation without analyzing the timing path.
Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. On/Off This option is automatically turned on when you turn on the I do not care (The outputs will be undefined) option. This option enables the RAM to output ‘don’t care’ or 'unknown' values for read-during-write operation without analyzing the timing path.
Parameter Settings: Output 2 (This tab is only available when you select two read/write ports)
Port A Read-During-Write Option What should the ‘q_a’ output be when reading from a memory location being written to?
  • New data
  • Old Data
 Specifies the output behavior when read-during-write occurs.
  • New Data—New data is available on the rising edge of the same clock cycle on which it was written.
  • Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds.
Port B Read-During-Write Option What should the ‘q_b’ output be when reading from a memory location being written to?
Get x’s for write masked bytes instead of old data when byte enable is used On/Off This option is automatically turned on when you select the New Data value. This option obtains ‘X’ on the masked byte.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data
 Specifies the initial content of the memory.
  • To initialize the memory to zero, select No, leave it blank.
  • To use a Memory Initialization File (.mif) or a Hexadecimal (Intel-format) File (.hex), select Yes, use this file for the memory content data.
Note: The configuration scheme of your device is Internal Configuration. In order to use memory initialization, you must select a single image configuration mode with memory initialization, for example the Single Compressed Image with Memory Initialization option. You can set the configuration mode on the Configuration page of the Device and Pin Options dialog box.
The initial content file should conform to which port's dimension?
  • PORT_A
  • PORT_B
 Specifies which port's dimension that the initial content file should conform to.
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